| Age | Commit message (Expand) | Author |
|---|
| 2010-09-13 | Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. | Gabe Black |
| 2010-08-25 | CPU: Print out traces for faluting inst when the flag ExecFaulting is set | Ali Saidi |
| 2010-08-13 | CPU: Add readBytes and writeBytes functions to the exec contexts. | Gabe Black |
| 2010-08-13 | CPU: Tidy up endianness handling for mmapped "IPR"s. | Gabe Black |
| 2010-03-23 | cpu: get rid of uncached access "events" | Steve Reinhardt |
| 2010-03-23 | cpu: fix exec tracing memory corruption bug | Steve Reinhardt |
| 2009-11-18 | m5: Fixed bug in atomic cpu destructor | Brad Beckmann |
| 2009-11-10 | Mem: Eliminate the NO_FAULT request flag. | Gabe Black |
| 2009-09-23 | arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh | Nathan Binkert |
| 2009-08-23 | Atomic CPU: Respect the NO_ACCESS request flag. | Gabe Black |
| 2009-06-04 | types: clean up types, especially signed vs unsigned | Nathan Binkert |
| 2009-05-26 | types: add a type for thread IDs and try to use it everywhere | Nathan Binkert |
| 2009-04-19 | Mem: Change isLlsc to isLLSC. | Gabe Black |
| 2009-04-19 | CPUs: Make the atomic CPU support locked memory accesses. | Gabe Black |
| 2009-04-19 | Memory: Rename LOCKED for load locked store conditional to LLSC. | Gabe Black |
| 2009-04-19 | CPU: If the simple CPU is already idle, just return from suspendContext, don'... | Gabe Black |
| 2009-04-08 | tlb: More fixing of unified TLB | Nathan Binkert |
| 2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black |
| 2009-03-11 | cpu: fix minor endian issue with trace output | Steve Reinhardt |
| 2009-02-25 | CPU: Don't fetch when executing a macroop. | Gabe Black |
| 2009-02-25 | CPU: Implement translateTiming which defers to translateAtomic, and convert t... | Gabe Black |
| 2009-02-25 | ISA: Replace the translate functions in the TLBs with translateAtomic. | Gabe Black |
| 2009-02-25 | CPU: Get rid of translate... functions from various interface classes. | Gabe Black |
| 2008-11-02 | Add in Context IDs to the simulator. From now on, cpuId is almost never used, | Lisa Hsu |
| 2008-11-02 | make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered | Lisa Hsu |
| 2008-10-12 | CPU: Explain why some code is commented out. | Gabe Black |
| 2008-10-12 | X86: Don't fetch in the simple CPU if you're in the ROM. | Gabe Black |
| 2008-10-09 | eventq: convert all usage of events to use the new API. | Nathan Binkert |
| 2008-08-11 | params: Convert the CPU objects to use the auto generated param structs. | Nathan Binkert |
| 2008-07-01 | Make the cached virtPort have a thread context so it can do everything that a... | Ali Saidi |
| 2008-07-01 | After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFra... | Ali Saidi |
| 2008-06-18 | AtomicSimpleCPU: Separate data stalls from instruction stalls. | Nathan Binkert |
| 2008-06-12 | CPU: Make the simple cpu trace data for loads/stores. | Gabe Black |
| 2008-02-14 | CPU: move the PC Events code to a place where the code won't be executed mult... | Ali Saidi |
| 2008-02-06 | Make the Event::description() a const function | Stephen Hines |
| 2008-01-02 | Additional comments and helper functions for PrintReq. | Steve Reinhardt |
| 2007-12-16 | CPU: Update where the simple cpus read their cpu id from the thread context t... | Ali Saidi |
| 2007-11-20 | Simple CPU fix simple mistake in translateDataWriteAddr. | Gabe Black |
| 2007-11-08 | AtomicSimpleCPU: Refactor resume() code to have a cleaner control path. | Ali Saidi |
| 2007-10-22 | CPU: Add functions to the "ExecContext"s that translate a given address. | Gabe Black |
| 2007-10-18 | CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases. | Ali Saidi |
| 2007-09-28 | Update stats for quiesced cycles | Ali Saidi |
| 2007-09-28 | Rename cycles() function to ticks() | Ali Saidi |
| 2007-08-26 | Merge with head | Gabe Black |
| 2007-08-26 | Simple CPU: Don't trace instructions that fault. Otherwise they show up twice. | Gabe Black |
| 2007-08-26 | Simple CPU: Added code that will split requests that cross block boundaries i... | Gabe Black |
| 2007-08-26 | Simple CPU: Make sure only instructions which complete without faulting are c... | Gabe Black |
| 2007-08-26 | Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. | Gabe Black |
| 2007-08-08 | Added fastmem option. | Vincentius Robby |
| 2007-08-04 | SimpleCPU: Add some DPRINTFs | Nathan Binkert |
