gem5 - gem5

Age	Commit message (Expand)	Author
2008-06-18	AtomicSimpleCPU: Separate data stalls from instruction stalls.	Nathan Binkert
2008-06-12	CPU: Make the simple cpu trace data for loads/stores.	Gabe Black
2008-02-14	CPU: move the PC Events code to a place where the code won't be executed mult...	Ali Saidi
2008-02-06	Make the Event::description() a const function	Stephen Hines
2008-01-02	Additional comments and helper functions for PrintReq.	Steve Reinhardt
2007-12-16	CPU: Update where the simple cpus read their cpu id from the thread context t...	Ali Saidi
2007-11-20	Simple CPU fix simple mistake in translateDataWriteAddr.	Gabe Black
2007-11-08	AtomicSimpleCPU: Refactor resume() code to have a cleaner control path.	Ali Saidi
2007-10-22	CPU: Add functions to the "ExecContext"s that translate a given address.	Gabe Black
2007-10-18	CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.	Ali Saidi
2007-09-28	Update stats for quiesced cycles	Ali Saidi
2007-09-28	Rename cycles() function to ticks()	Ali Saidi
2007-08-26	Merge with head	Gabe Black
2007-08-26	Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.	Gabe Black
2007-08-26	Simple CPU: Added code that will split requests that cross block boundaries i...	Gabe Black
2007-08-26	Simple CPU: Make sure only instructions which complete without faulting are c...	Gabe Black
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-08-08	Added fastmem option.	Vincentius Robby
2007-08-04	SimpleCPU: Add some DPRINTFs	Nathan Binkert
2007-07-29	Merge Gabe's changes from head.	Steve Reinhardt
2007-07-28	Turn the instruction tracing code into pluggable sim objects.	Gabe Black
2007-07-28	AtomicSimpleCPU: fix inadvertent loss of endian conversion on read.	Steve Reinhardt
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-06-30	Make CPU models use new LoadLockedReq/StoreCondReq commands.	Steve Reinhardt
2007-06-30	Event descriptions should not end in "event"	Steve Reinhardt
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-06-19	Make branches work by repopulating the predecoder every time through. This is...	Gabe Black
2007-06-12	Make microOp vs microop and macroOp vs macroop capitilization consistent.	Gabe Black
2007-05-18	Changes to make simple cpu handle pcs appropriately for x86	Gabe Black
2007-04-10	Even if you don't want to fetch more bytes, make sure you handle a fault.	Gabe Black
2007-03-15	Merge zizzer.eecs.umich.edu:/bk/newmem	Gabe Black
2007-03-15	Make the predecoder an object with it's own switched header file. Start addin...	Gabe Black
2007-03-11	Make sttw and sttwa use the twin memory operations.	Gabe Black
2007-03-09	Two fixes:	Kevin Lim
2007-03-02	make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way a...	Ali Saidi
2007-02-12	some forgotten commits	Ali Saidi
2007-02-12	Merge zizzer:/bk/newmem	Ali Saidi
2007-02-12	rename store conditional stuff as extra data so it can be used for conditiona...	Ali Saidi
2007-02-12	Move store conditional result checking from SimpleAtomicCpu write	Steve Reinhardt
2007-02-07	Make memory commands dense again to avoid cache stat table explosion.	Steve Reinhardt
2007-01-16	Modify ISA and staticInst to support a IsFirstMicroOp flag	Ali Saidi
2006-12-04	More changes to get SPARC fs closer. Now at 1.2M cycles before difference	Ali Saidi
2006-11-29	Merge zizzer:/bk/newmem	Ali Saidi
2006-11-29	Add support for mmapped iprs to atomic cpu	Ali Saidi
2006-11-29	Change the connecting of the physPort and virtPort to the memory object below...	Kevin Lim
2006-11-17	Make an initialization pass for the thread context and set the [phys,virt]Por...	Ron Dreslinski
2006-11-14	Make cpu's capable of having a phase shift	Ron Dreslinski
2006-11-13	Changes needed for a bus from CPU->L1	Ron Dreslinski
2006-11-13	Make CPU models signal to update the snoop ranges	Ron Dreslinski