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Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
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These recordEvent() calls could cause crashes since they
access the req pointer after it's potentially been
deleted during a failed translation call. (Similar
problem to the traceData bug fixed in the previous cset.)
Moving them above the translation call (as was done
recentlyi in cset 8b2b8e5e7d35) avoids the crash
but doesn't work, since at that point we don't know if
the access is uncached or not.
It's not clear why these calls are there, and no one
seems to use them, so we'll just delete them. If they
are needed, they should be moved to somewhere that's
guaranteed to be after the translation completes but
before the request is possibly deleted, e.g., in
finishTranslation().
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Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.
It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical. Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.
This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition. It also moves those calls above
the translation calls to eliminate the crashes.
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don't assert.
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(no functional change)
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If the CPL changes mid macroop, the end of the instruction might not be
priveleged enough to execute the beginning.
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the timing simple CPU to use it.
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the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
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across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
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For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
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A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
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a newly created one can.
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not_idle_fraction/notIdleFraction statistic is really wrong.
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
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Separate simulation of icache stalls and dat stalls.
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multiple times if an instruction faults.
--HG--
extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
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--HG--
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--HG--
extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
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to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
--HG--
extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
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--HG--
extra : convert_revision : 6a6a7d05f62d9d9868be0707e4dc186a5f7ecf7d
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--HG--
extra : convert_revision : f27bb96850e7fb0252fb1f47c3d0860705c32884
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--HG--
extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397
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--HG--
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--HG--
extra : convert_revision : 703ba58f156c9f2677b020f05d36bc1e3ae0b9e5
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--HG--
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--HG--
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--HG--
extra : convert_revision : 4446d9544d58bdadbd24d8322bb63016a32aa2b8
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into multiple memory access.
--HG--
extra : convert_revision : 600f79f32ef30a6e1db951503bcfe8cd332858d1
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counted.
--HG--
extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
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--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
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Lets CPU accesses to physical memory bypass Bus.
--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
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--HG--
extra : convert_revision : 5fdd5a9595c3e5d6ce5f9e8c9af0a8e6c857551c
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