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path: root/src/cpu/simple/atomic.cc
AgeCommit message (Expand)Author
2016-06-06pwr: Low-power idle power state for idle CPUsDavid Guillen Fandos
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2014-12-09power: Low-power idle power state for idle CPUsAkash Bagdia
2015-07-19cpu: Fix LLSC atomic CPU wakeupKrishnendra Nathella
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
2015-09-30cpu,isa,mem: Add per-thread wakeup logicMitch Hayenga
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-09-30config,cpu: Add SMT support to Atomic and Timing CPUsMitch Hayenga
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-04-03cpu: fix system total instructions accountingNikos Nikoleris
2015-03-23mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMWSteve Reinhardt
2015-02-11mem: restructure Packet cmd initialization a bit moreSteve Reinhardt
2015-01-25sim: Clean up InstRecordAli Saidi
2015-01-20cpu: commit probe notification on every microop or macroopNikos Nikoleris
2014-12-05cpu: Only check for PC events on instruction boundaries.Gabe Black
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-11-14arm: Fixes based on UBSan and static analysisAndreas Hansson
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-10-16cpu: Probe points for basic PMU statsAndreas Sandberg
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-20cpu: use probes infrastructure to do simpoint profilingDam Sunwoo
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24cpu: remove faulty simpoint basic block inst count assertionDam Sunwoo
2013-08-19cpu: Accurately count idle cycles for simple cpuLena Olson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg
2013-01-07cpu: Make sure that a drained atomic CPU isn't executing ucodeAndreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Correctly call parent on switchOut() and takeOverFrom()Andreas Sandberg
2013-01-07cpu: Check that the memory system is in the correct modeAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-06-05cpu: Don't init simple and inorder CPUs if they are defered.Anthony Gutierrez
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-04-03Atomic: Remove the physmem_port and access memory directlyAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-30CPU: Unify initMemProxies across CPUs and simulation modesAndreas Hansson
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