summaryrefslogtreecommitdiff
path: root/src/cpu/simple/timing.cc
AgeCommit message (Expand)Author
2007-08-26Merge with headGabe Black
2007-08-26Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.Gabe Black
2007-08-26Simple CPU: Make sure only instructions which complete without faulting are c...Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-07-02Couple more minor bug fixes for FS timing mode.Steve Reinhardt
2007-07-02Fix a couple LL/SC bugs that only affected timing mode.Steve Reinhardt
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-18fix bug in timing cpu. getTime() is the time the requset was created, not the...Ali Saidi
2007-05-20Add new EventWrapper constructor that takes a Tick valueSteve Reinhardt
2007-05-07the bridge never returns false when recvTiming() is called on its ports now, ...Ali Saidi
2007-03-11Make sttw and sttwa use the twin memory operations.Gabe Black
2007-03-10I thought this code got deleted, but since it hasn't I've moved it to a place...Ali Saidi
2007-03-09Two fixes:Kevin Lim
2007-03-02make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way a...Ali Saidi
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
2006-11-29Change the connecting of the physPort and virtPort to the memory object below...Kevin Lim
2006-11-17Make an initialization pass for the thread context and set the [phys,virt]Por...Ron Dreslinski
2006-11-14Merge zizzer:/bk/newmemRon Dreslinski
2006-11-14Various fixes to delete packet and request a little better.Kevin Lim
2006-11-14Make cpu's capable of having a phase shiftRon Dreslinski
2006-11-13Make CPU models signal to update the snoop rangesRon Dreslinski
2006-11-11Get rid of the ParamContext for pseudo instructions and moveNathan Binkert
2006-11-06Clean up clock phase drift code a bit.Kevin Lim
2006-11-01Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-31Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes mor...Gabe Black
2006-10-23Don't let interupts interupt microcode at undesired points.Gabe Black
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
2006-10-17Fixes for uni-coherence in timing mode for FS.Ron Dreslinski
2006-10-12Merge zizzer:/bk/newmemLisa Hsu
2006-10-11some drain changes in timing (kevin's) and some memory mode assertion changes...Lisa Hsu
2006-10-09Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-10-09Fix caches plus sampling switch over.Kevin Lim
2006-10-08Fixes for functional path.Ron Dreslinski
2006-10-08Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().Steve Reinhardt
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
2006-10-08Rename some vars for clarity.Steve Reinhardt
2006-10-08Record numCycles properly.Kevin Lim
2006-10-02Be sure to set progress interval.Kevin Lim
2006-07-20Enforce the timing cpu ticking at it's clock rateAli Saidi
2006-07-14Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-12memory mode information now contained in system objectAli Saidi
2006-07-12Updates for serialization. As long as the tickEvent doesn't need to be seria...Kevin Lim
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 21:57:01 +0000