| Age | Commit message (Expand) | Author |
|---|
| 2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
| 2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
| 2015-09-30 | config,cpu: Add SMT support to Atomic and Timing CPUs | Mitch Hayenga |
| 2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
| 2015-04-03 | cpu: fix system total instructions accounting | Nikos Nikoleris |
| 2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
| 2015-02-03 | cpu: Ensure timing CPU sinks response before sending new request | Andreas Hansson |
| 2015-01-25 | sim: Clean up InstRecord | Ali Saidi |
| 2015-01-22 | mem: Clean up Request initialisation | Andreas Hansson |
| 2014-12-05 | cpu: Only check for PC events on instruction boundaries. | Gabe Black |
| 2014-12-02 | mem: Assume all dynamic packet data is array allocated | Andreas Hansson |
| 2014-11-12 | arm: Fix timing wakeup with LLSC | Ali Saidi |
| 2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
| 2014-10-16 | cpu: Probe points for basic PMU stats | Andreas Sandberg |
| 2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
| 2014-09-19 | arch: Pass faults by const reference where possible | Andreas Hansson |
| 2014-05-13 | mem: Refactor assignment of Packet types | Curtis Dunham |
| 2014-01-24 | cpu: Add support for instructions that zero cache lines. | Ali Saidi |
| 2014-01-24 | cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo... | Ali Saidi |
| 2014-01-24 | mem: per-thread cache occupancy and per-block ages | Dam Sunwoo |
| 2014-01-24 | mem: track per-request latencies and access depths in the cache hierarchy | Matt Horsnell |
| 2013-08-19 | cpu: Accurately count idle cycles for simple cpu | Lena Olson |
| 2013-08-19 | cpu: Fix timing CPU drain check | Andreas Hansson |
| 2013-07-18 | mem: Set the cache line size on a system level | Andreas Hansson |
| 2013-04-22 | sim: separate nextCycle() and clockEdge() in clockedObjects | Dam Sunwoo |
| 2013-02-15 | sim: Add a system-global option to bypass caches | Andreas Sandberg |
| 2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
| 2013-01-07 | cpu: Unify the serialization code for all of the CPU models | Andreas Sandberg |
| 2013-01-07 | cpu: Make sure that a drained timing CPU isn't executing ucode | Andreas Sandberg |
| 2013-01-07 | cpu: Rename defer_registration->switched_out | Andreas Sandberg |
| 2013-01-07 | cpu: Correctly call parent on switchOut() and takeOverFrom() | Andreas Sandberg |
| 2013-01-07 | cpu: Check that the memory system is in the correct mode | Andreas Sandberg |
| 2012-11-02 | sim: Move the draining interface into a separate base class | Andreas Sandberg |
| 2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
| 2012-08-28 | Clock: Rework clocks to avoid tick-to-cycle transformations | Andreas Hansson |
| 2012-08-22 | Packet: Remove NACKs from packet and its use in endpoints | Andreas Hansson |
| 2012-08-15 | O3,ARM: fix some problems with drain/switchout functionality and add Drain DP... | Anthony Gutierrez |
| 2012-06-05 | cpu: Don't init simple and inorder CPUs if they are defered. | Anthony Gutierrez |
| 2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
| 2012-04-14 | MEM: Remove the Broadcast destination from the packet | Andreas Hansson |
| 2012-04-14 | MEM: Separate snoops and normal memory requests/responses | Andreas Hansson |
| 2012-03-30 | CPU: Unify initMemProxies across CPUs and simulation modes | Andreas Hansson |
| 2012-02-24 | CPU: Round-two unifying instr/data CPU ports across models | Andreas Hansson |
| 2012-02-12 | mem: Add a master ID to each request object. | Ali Saidi |
| 2012-01-31 | Merge with head, hopefully the last time for this batch. | Gabe Black |
| 2012-01-31 | clang: Enable compiling gem5 using clang 2.9 and 3.0 | Koan-Sin Tan |
| 2012-01-28 | Merge with the main repo. | Gabe Black |
| 2012-01-17 | MEM: Simplify ports by removing EventManager | Andreas Hansson |
| 2012-01-17 | CPU: Moving towards a more general port across CPU models | Andreas Hansson |
| 2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson |
