| Age | Commit message (Expand) | Author |
|---|
| 2012-01-28 | Merge with the main repo. | Gabe Black |
| 2012-01-17 | MEM: Simplify ports by removing EventManager | Andreas Hansson |
| 2012-01-17 | CPU: Moving towards a more general port across CPU models | Andreas Hansson |
| 2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson |
| 2011-11-18 | SE/FS: Get rid of FULL_SYSTEM in the CPU directory. | Gabe Black |
| 2011-11-01 | SE/FS: Expose the same methods on the CPUs in SE and FS modes. | Gabe Black |
| 2011-08-07 | Translation: Use a pointer type as the template argument. | Gabe Black |
| 2011-07-02 | ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. | Gabe Black |
| 2011-07-02 | ExecContext: Get rid of the now unused read/write templated functions. | Gabe Black |
| 2011-05-04 | CPU: Add some useful debug message to the timing simple cpu. | Ali Saidi |
| 2011-05-04 | CPU: Fix a case where timing simple cpu faults can nest. | Ali Saidi |
| 2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert |
| 2011-04-15 | includes: sort all includes | Nathan Binkert |
| 2011-03-17 | ARM: Detect and skip udelay() functions in linux kernel. | Ali Saidi |
| 2011-03-01 | Spelling: Fix the a spelling error by changing mmaped to mmapped. | Gabe Black |
| 2011-02-11 | SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk o... | Ali Saidi |
| 2011-02-06 | TimingSimpleCPU: split data sender state fix | Joel Hestness |
| 2011-02-06 | mcpat: Adds McPAT performance counters | Joel Hestness |
| 2011-01-07 | Replace curTick global variable with accessor functions. | Steve Reinhardt |
| 2010-11-15 | CPU: Fix bug when a split transaction is issued to a faster cache | Ali Saidi |
| 2010-11-08 | ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. | Ali Saidi |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black |
| 2010-09-30 | CPU/Cache: Fix some errors exposed by valgrind | Ali Saidi |
| 2010-09-13 | Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. | Gabe Black |
| 2010-08-25 | CPU: Print out traces for faluting inst when the flag ExecFaulting is set | Ali Saidi |
| 2010-08-13 | Merge with head. | Gabe Black |
| 2010-08-13 | CPU: Add readBytes and writeBytes functions to the exec contexts. | Gabe Black |
| 2010-08-12 | TimingSimpleCPU: fix NO_ACCESS memory op handling | Joel Hestness |
| 2010-03-23 | cpu: get rid of uncached access "events" | Steve Reinhardt |
| 2010-03-23 | cpu: fix exec tracing memory corruption bug | Steve Reinhardt |
| 2010-03-21 | TimingSimpleCPU: Fixed uncacacheable request read bug | Brad Beckmann |
| 2010-02-12 | BaseDynInst: Make the TLB translation timing instead of atomic. | Timothy M. Jones |
| 2009-11-10 | Mem: Eliminate the NO_FAULT request flag. | Gabe Black |
| 2009-09-23 | arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh | Nathan Binkert |
| 2009-06-04 | types: clean up types, especially signed vs unsigned | Nathan Binkert |
| 2009-05-26 | types: add a type for thread IDs and try to use it everywhere | Nathan Binkert |
| 2009-04-19 | Mem: Change isLlsc to isLLSC. | Gabe Black |
| 2009-04-19 | Memory: Rename LOCKED for load locked store conditional to LLSC. | Gabe Black |
| 2009-04-19 | CPU: If the simple CPU is already idle, just return from suspendContext, don'... | Gabe Black |
| 2009-04-08 | tlb: More fixing of unified TLB | Nathan Binkert |
| 2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black |
| 2009-03-11 | cpu: fix minor endian issue with trace output | Steve Reinhardt |
| 2009-02-25 | CPU: Don't fetch when executing a macroop. | Gabe Black |
| 2009-02-25 | CPU: Implement translateTiming which defers to translateAtomic, and convert t... | Gabe Black |
| 2009-02-25 | ISA: Replace the translate functions in the TLBs with translateAtomic. | Gabe Black |
| 2009-02-25 | CPU: Get rid of translate... functions from various interface classes. | Gabe Black |
| 2008-11-13 | CPU: Refactor read/write in the simple timing CPU. | Gabe Black |
| 2008-11-09 | CPU: Make unaligned accesses work in the timing simple CPU. | Gabe Black |
| 2008-11-09 | X86: Make the timing simple CPU handle variable length instructions. | Gabe Black |
| 2008-11-02 | Add in Context IDs to the simulator. From now on, cpuId is almost never used, | Lisa Hsu |
