gem5 - gem5

Age	Commit message (Expand)	Author
2007-11-08	TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.	Ali Saidi
2007-10-22	CPU: Add functions to the "ExecContext"s that translate a given address.	Gabe Black
2007-10-18	CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.	Ali Saidi
2007-10-01	CPU: fix sparc_fs booting with SimpleTimingCPU.	Ali Saidi
2007-09-28	Update stats for quiesced cycles	Ali Saidi
2007-09-28	Rename cycles() function to ticks()	Ali Saidi
2007-09-28	Update statistics to use cycles properly instead of ticks	Ali Saidi
2007-08-26	Merge with head	Gabe Black
2007-08-26	Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.	Gabe Black
2007-08-26	Simple CPU: Make sure only instructions which complete without faulting are c...	Gabe Black
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-07-29	Merge Gabe's changes from head.	Steve Reinhardt
2007-07-28	Turn the instruction tracing code into pluggable sim objects.	Gabe Black
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-07-02	Couple more minor bug fixes for FS timing mode.	Steve Reinhardt
2007-07-02	Fix a couple LL/SC bugs that only affected timing mode.	Steve Reinhardt
2007-06-30	Make CPU models use new LoadLockedReq/StoreCondReq commands.	Steve Reinhardt
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-06-18	fix bug in timing cpu. getTime() is the time the requset was created, not the...	Ali Saidi
2007-05-20	Add new EventWrapper constructor that takes a Tick value	Steve Reinhardt
2007-05-07	the bridge never returns false when recvTiming() is called on its ports now, ...	Ali Saidi
2007-03-11	Make sttw and sttwa use the twin memory operations.	Gabe Black
2007-03-10	I thought this code got deleted, but since it hasn't I've moved it to a place...	Ali Saidi
2007-03-09	Two fixes:	Kevin Lim
2007-03-02	make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way a...	Ali Saidi
2007-02-12	rename store conditional stuff as extra data so it can be used for conditiona...	Ali Saidi
2007-02-07	Make memory commands dense again to avoid cache stat table explosion.	Steve Reinhardt
2006-11-29	Change the connecting of the physPort and virtPort to the memory object below...	Kevin Lim
2006-11-17	Make an initialization pass for the thread context and set the [phys,virt]Por...	Ron Dreslinski
2006-11-14	Merge zizzer:/bk/newmem	Ron Dreslinski
2006-11-14	Various fixes to delete packet and request a little better.	Kevin Lim
2006-11-14	Make cpu's capable of having a phase shift	Ron Dreslinski
2006-11-13	Make CPU models signal to update the snoop ranges	Ron Dreslinski
2006-11-11	Get rid of the ParamContext for pseudo instructions and move	Nathan Binkert
2006-11-06	Clean up clock phase drift code a bit.	Kevin Lim
2006-11-01	Merge zizzer.eecs.umich.edu:/bk/newmem/	Gabe Black
2006-10-31	Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...	Kevin Lim
2006-10-31	Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes mor...	Gabe Black
2006-10-23	Don't let interupts interupt microcode at undesired points.	Gabe Black
2006-10-20	Use PacketPtr everywhere	Nathan Binkert
2006-10-19	refactor code for the packet, get rid of packet_impl.hh	Nathan Binkert
2006-10-17	Fixes for uni-coherence in timing mode for FS.	Ron Dreslinski
2006-10-12	Merge zizzer:/bk/newmem	Lisa Hsu
2006-10-11	some drain changes in timing (kevin's) and some memory mode assertion changes...	Lisa Hsu
2006-10-09	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-10-09	Fix caches plus sampling switch over.	Kevin Lim
2006-10-08	Fixes for functional path.	Ron Dreslinski
2006-10-08	Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().	Steve Reinhardt
2006-10-08	Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)	Steve Reinhardt