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path: root/src/cpu/simple/timing.cc
AgeCommit message (Expand)Author
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-07-15Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.Steve Reinhardt
2008-07-01Make the cached virtPort have a thread context so it can do everything that a...Ali Saidi
2008-07-01After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFra...Ali Saidi
2008-06-12CPU: Make the simple cpu trace data for loads/stores.Gabe Black
2008-02-14CPU: move the PC Events code to a place where the code won't be executed mult...Ali Saidi
2008-02-06Make the Event::description() a const functionStephen Hines
2008-02-05Add base ARM code to M5Stephen Hines
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
2007-12-16CPU: Update where the simple cpus read their cpu id from the thread context t...Ali Saidi
2007-11-08TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.Ali Saidi
2007-10-22CPU: Add functions to the "ExecContext"s that translate a given address.Gabe Black
2007-10-18CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.Ali Saidi
2007-10-01CPU: fix sparc_fs booting with SimpleTimingCPU.Ali Saidi
2007-09-28Update stats for quiesced cyclesAli Saidi
2007-09-28Rename cycles() function to ticks()Ali Saidi
2007-09-28Update statistics to use cycles properly instead of ticksAli Saidi
2007-08-26Merge with headGabe Black
2007-08-26Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.Gabe Black
2007-08-26Simple CPU: Make sure only instructions which complete without faulting are c...Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-07-02Couple more minor bug fixes for FS timing mode.Steve Reinhardt
2007-07-02Fix a couple LL/SC bugs that only affected timing mode.Steve Reinhardt
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-18fix bug in timing cpu. getTime() is the time the requset was created, not the...Ali Saidi
2007-05-20Add new EventWrapper constructor that takes a Tick valueSteve Reinhardt
2007-05-07the bridge never returns false when recvTiming() is called on its ports now, ...Ali Saidi
2007-03-11Make sttw and sttwa use the twin memory operations.Gabe Black
2007-03-10I thought this code got deleted, but since it hasn't I've moved it to a place...Ali Saidi
2007-03-09Two fixes:Kevin Lim
2007-03-02make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way a...Ali Saidi
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
2006-11-29Change the connecting of the physPort and virtPort to the memory object below...Kevin Lim
2006-11-17Make an initialization pass for the thread context and set the [phys,virt]Por...Ron Dreslinski
2006-11-14Merge zizzer:/bk/newmemRon Dreslinski
2006-11-14Various fixes to delete packet and request a little better.Kevin Lim
2006-11-14Make cpu's capable of having a phase shiftRon Dreslinski
2006-11-13Make CPU models signal to update the snoop rangesRon Dreslinski
2006-11-11Get rid of the ParamContext for pseudo instructions and moveNathan Binkert
2006-11-06Clean up clock phase drift code a bit.Kevin Lim
2006-11-01Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-31Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes mor...Gabe Black
2006-10-23Don't let interupts interupt microcode at undesired points.Gabe Black
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