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path: root/src/cpu/simple/timing.cc
AgeCommit message (Collapse)Author
2010-09-30CPU/Cache: Fix some errors exposed by valgrindAli Saidi
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
2010-08-25CPU: Print out traces for faluting inst when the flag ExecFaulting is setAli Saidi
2010-08-13Merge with head.Gabe Black
2010-08-13CPU: Add readBytes and writeBytes functions to the exec contexts.Gabe Black
2010-08-12TimingSimpleCPU: fix NO_ACCESS memory op handlingJoel Hestness
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs to handle the case where the current status of the CPU is Running and not DcacheWaitResponse or DTBWaitResponse
2010-03-23cpu: get rid of uncached access "events"Steve Reinhardt
These recordEvent() calls could cause crashes since they access the req pointer after it's potentially been deleted during a failed translation call. (Similar problem to the traceData bug fixed in the previous cset.) Moving them above the translation call (as was done recentlyi in cset 8b2b8e5e7d35) avoids the crash but doesn't work, since at that point we don't know if the access is uncached or not. It's not clear why these calls are there, and no one seems to use them, so we'll just delete them. If they are needed, they should be moved to somewhere that's guaranteed to be after the translation completes but before the request is possibly deleted, e.g., in finishTranslation().
2010-03-23cpu: fix exec tracing memory corruption bugSteve Reinhardt
Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. It turns out that there was never a need to access traceData after initiating the translation, as the traced data was always available earlier; this ordering was merely historical. Furthermore, traceData->setAddress() and traceData->setData() were being called both from the CPU model and the ISA definition, often redundantly. This patch standardizes all setAddress and setData calls for memory instructions to be in the CPU models and not in the ISA definition. It also moves those calls above the translation calls to eliminate the crashes.
2010-03-21TimingSimpleCPU: Fixed uncacacheable request read bugBrad Beckmann
Previously the recording of an uncached read occurred after the request was possibly deleted within the translateTiming function.
2010-02-12BaseDynInst: Make the TLB translation timing instead of atomic.Timothy M. Jones
This initiates a timing translation and passes the read or write on to the processor before waiting for it to finish. Once the translation is finished, the instruction's state is updated via the 'finish' function. A new DataTranslation class is created to handle this. The idea is taken from the implementation of timing translations in TimingSimpleCPU by Gabe Black. This patch also separates out the timing translations from this CPU and uses the new DataTranslation class.
2009-11-10Mem: Eliminate the NO_FAULT request flag.Gabe Black
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-04-19CPU: If the simple CPU is already idle, just return from suspendContext, ↵Gabe Black
don't assert.
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-03-11cpu: fix minor endian issue with trace outputSteve Reinhardt
(no functional change)
2009-02-25CPU: Don't fetch when executing a macroop.Gabe Black
If the CPL changes mid macroop, the end of the instruction might not be priveleged enough to execute the beginning.
2009-02-25CPU: Implement translateTiming which defers to translateAtomic, and convert ↵Gabe Black
the timing simple CPU to use it.
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2008-11-13CPU: Refactor read/write in the simple timing CPU.Gabe Black
2008-11-09CPU: Make unaligned accesses work in the timing simple CPU.Gabe Black
2008-11-09X86: Make the timing simple CPU handle variable length instructions.Gabe Black
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
2008-10-27CPU: The API change to EventWrapper did not get propagated to the entirety ↵Clint Smullen
of TimingSimpleCPU. The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning. Signed-off By: Ali Saidi
2008-10-12X86: Don't fetch in the simple CPU if you're in the ROM.Gabe Black
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5.
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end.
2008-07-15Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.Steve Reinhardt
2008-07-01Make the cached virtPort have a thread context so it can do everything that ↵Ali Saidi
a newly created one can.
2008-07-01After a checkpoint (and thus a stats reset), the ↵Ali Saidi
not_idle_fraction/notIdleFraction statistic is really wrong. The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing with Port::Status, but _status seems a bit strage too.
2008-06-12CPU: Make the simple cpu trace data for loads/stores.Gabe Black
2008-02-14CPU: move the PC Events code to a place where the code won't be executed ↵Ali Saidi
multiple times if an instruction faults. --HG-- extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
2008-02-06Make the Event::description() a const functionStephen Hines
--HG-- extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
2008-02-05Add base ARM code to M5Stephen Hines
--HG-- extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
--HG-- extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
2007-12-16CPU: Update where the simple cpus read their cpu id from the thread context ↵Ali Saidi
to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations. --HG-- extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
2007-11-08TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.Ali Saidi
--HG-- extra : convert_revision : a305cf9dcaca5ed3b97499a5e24c511f4416125a
2007-10-22CPU: Add functions to the "ExecContext"s that translate a given address.Gabe Black
--HG-- extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397
2007-10-18CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.Ali Saidi
--HG-- extra : convert_revision : 6d025764682181b1f67df3b1d8d1d59099136df7
2007-10-01CPU: fix sparc_fs booting with SimpleTimingCPU.Ali Saidi
--HG-- extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885
2007-09-28Update stats for quiesced cyclesAli Saidi
--HG-- extra : convert_revision : 703ba58f156c9f2677b020f05d36bc1e3ae0b9e5
2007-09-28Rename cycles() function to ticks()Ali Saidi
--HG-- extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
2007-09-28Update statistics to use cycles properly instead of ticksAli Saidi
--HG-- extra : convert_revision : 62911280b631ef24720f9ce701d1c19a9b8a9784
2007-08-26Merge with headGabe Black
--HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6