| Age | Commit message (Expand) | Author |
|---|
| 2013-03-26 | cpu: Remove CpuPort and use MasterPort in the CPU classes | Andreas Hansson |
| 2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
| 2013-01-07 | cpu: Make sure that a drained timing CPU isn't executing ucode | Andreas Sandberg |
| 2012-11-02 | sim: Move the draining interface into a separate base class | Andreas Sandberg |
| 2012-09-25 | ARM: Squash outstanding walks when instructions are squashed. | Ali Saidi |
| 2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
| 2012-08-28 | Clock: Rework clocks to avoid tick-to-cycle transformations | Andreas Hansson |
| 2012-07-09 | Port: Align port names in C++ and Python | Andreas Hansson |
| 2012-07-09 | Port: Move retry from port base class to Master/SlavePort | Andreas Hansson |
| 2012-06-08 | Timing CPU: Remove a redundant port pointer | Andreas Hansson |
| 2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
| 2012-04-14 | MEM: Separate snoops and normal memory requests/responses | Andreas Hansson |
| 2012-02-24 | CPU: Round-two unifying instr/data CPU ports across models | Andreas Hansson |
| 2012-01-31 | clang: Enable compiling gem5 using clang 2.9 and 3.0 | Koan-Sin Tan |
| 2012-01-17 | CPU: Moving towards a more general port across CPU models | Andreas Hansson |
| 2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson |
| 2011-07-02 | ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. | Gabe Black |
| 2011-07-02 | ExecContext: Get rid of the now unused read/write templated functions. | Gabe Black |
| 2011-04-15 | includes: sort all includes | Nathan Binkert |
| 2011-02-11 | SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk o... | Ali Saidi |
| 2011-02-11 | O3: Enhance data address translation by supporting hardware page table walkers. | Giacomo Gabrielli |
| 2010-11-15 | CPU: Fix bug when a split transaction is issued to a faster cache | Ali Saidi |
| 2010-08-13 | CPU: Add readBytes and writeBytes functions to the exec contexts. | Gabe Black |
| 2010-02-12 | BaseDynInst: Make the TLB translation timing instead of atomic. | Timothy M. Jones |
| 2009-04-08 | tlb: More fixing of unified TLB | Nathan Binkert |
| 2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black |
| 2009-02-25 | CPU: Implement translateTiming which defers to translateAtomic, and convert t... | Gabe Black |
| 2009-02-25 | CPU: Get rid of translate... functions from various interface classes. | Gabe Black |
| 2008-11-13 | CPU: Refactor read/write in the simple timing CPU. | Gabe Black |
| 2008-11-09 | CPU: Make unaligned accesses work in the timing simple CPU. | Gabe Black |
| 2008-10-27 | CPU: The API change to EventWrapper did not get propagated to the entirety o... | Clint Smullen |
| 2008-10-09 | eventq: convert all usage of events to use the new API. | Nathan Binkert |
| 2008-08-11 | params: Convert the CPU objects to use the auto generated param structs. | Nathan Binkert |
| 2008-07-01 | After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFra... | Ali Saidi |
| 2008-02-06 | Make the Event::description() a const function | Stephen Hines |
| 2008-01-02 | Additional comments and helper functions for PrintReq. | Steve Reinhardt |
| 2007-10-22 | CPU: Add functions to the "ExecContext"s that translate a given address. | Gabe Black |
| 2007-10-18 | CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases. | Ali Saidi |
| 2007-10-01 | CPU: fix sparc_fs booting with SimpleTimingCPU. | Ali Saidi |
| 2007-06-30 | Event descriptions should not end in "event" | Steve Reinhardt |
| 2007-05-21 | Change getDeviceAddressRanges to use bool for snoop arg. | Steve Reinhardt |
| 2007-05-20 | Add new EventWrapper constructor that takes a Tick value | Steve Reinhardt |
| 2007-03-09 | Two fixes: | Kevin Lim |
| 2006-12-15 | little fixes i noticed while searching for reason for address range issues (b... | Lisa Hsu |
| 2006-11-13 | Make CPU models signal to update the snoop ranges | Ron Dreslinski |
| 2006-10-31 | Ports now have a pointer to the MemObject that owns it (can be NULL). | Kevin Lim |
| 2006-10-20 | Use PacketPtr everywhere | Nathan Binkert |
| 2006-10-09 | Merge ktlim@zizzer:/bk/newmem | Kevin Lim |
| 2006-10-09 | Have cpus send snoop ranges | Ron Dreslinski |
| 2006-10-08 | Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) | Steve Reinhardt |
