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path: root/src/cpu/simple/timing.hh
AgeCommit message (Expand)Author
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
2015-10-12misc: Add explicit overrides and fix other clang >= 3.5 issuesAndreas Hansson
2015-10-12misc: Remove redundant compiler-specific definesAndreas Hansson
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-09-30config,cpu: Add SMT support to Atomic and Timing CPUsMitch Hayenga
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-01-22mem: Clean up Request initialisationAndreas Hansson
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-10-16cpu: Probe points for basic PMU statsAndreas Sandberg
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2013-08-20cpu: Fix timing CPU isDrained comment formattingAndreas Hansson
2013-08-19cpu: Fix timing CPU drain checkAndreas Hansson
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-01-07cpu: Make sure that a drained timing CPU isn't executing ucodeAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-06-08Timing CPU: Remove a redundant port pointerAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-17CPU: Moving towards a more general port across CPU modelsAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2011-07-02ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.Gabe Black
2011-07-02ExecContext: Get rid of the now unused read/write templated functions.Gabe Black
2011-04-15includes: sort all includesNathan Binkert
2011-02-11SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk o...Ali Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2010-11-15CPU: Fix bug when a split transaction is issued to a faster cacheAli Saidi
2010-08-13CPU: Add readBytes and writeBytes functions to the exec contexts.Gabe Black
2010-02-12BaseDynInst: Make the TLB translation timing instead of atomic.Timothy M. Jones
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-02-25CPU: Implement translateTiming which defers to translateAtomic, and convert t...Gabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2008-11-13CPU: Refactor read/write in the simple timing CPU.Gabe Black
2008-11-09CPU: Make unaligned accesses work in the timing simple CPU.Gabe Black
2008-10-27CPU: The API change to EventWrapper did not get propagated to the entirety o...Clint Smullen
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
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