Age | Commit message (Expand) | Author |
2019-12-11 | cpu: Fix coding style (byteEnable->byte_enable) | Giacomo Travaglini |
2019-09-23 | cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor> | Jordi Vaquero |
2019-08-28 | cpu: Make get(Data|Inst)Port return a Port and not a MasterPort. | Gabe Black |
2019-07-16 | cpu: isDrained renamed to isCpuDrained | Giacomo Travaglini |
2019-05-11 | cpu,mem: Add support for partial loads/stores and wide mem. accesses | Giacomo Gabrielli |
2019-02-08 | cpu: support atomic memory request type with AtomicOpFunctor | Tuan Ta |
2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
2017-06-20 | cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
2016-08-15 | cpu, arch: fix the type used for the request flags | Nikos Nikoleris |
2016-02-10 | mem: Deduce if cache should forward snoops | Andreas Hansson |
2016-01-17 | cpu. arch: add initiateMemRead() to ExecContext interface | Steve Reinhardt |
2015-10-12 | misc: Add explicit overrides and fix other clang >= 3.5 issues | Andreas Hansson |
2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
2015-09-30 | config,cpu: Add SMT support to Atomic and Timing CPUs | Mitch Hayenga |
2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
2015-01-22 | mem: Clean up Request initialisation | Andreas Hansson |
2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
2014-10-16 | cpu: Probe points for basic PMU stats | Andreas Sandberg |
2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
2014-09-19 | arch: Pass faults by const reference where possible | Andreas Hansson |
2014-01-24 | cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo... | Ali Saidi |
2013-08-20 | cpu: Fix timing CPU isDrained comment formatting | Andreas Hansson |
2013-08-19 | cpu: Fix timing CPU drain check | Andreas Hansson |
2013-03-26 | cpu: Remove CpuPort and use MasterPort in the CPU classes | Andreas Hansson |
2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
2013-01-07 | cpu: Make sure that a drained timing CPU isn't executing ucode | Andreas Sandberg |
2012-11-02 | sim: Move the draining interface into a separate base class | Andreas Sandberg |
2012-09-25 | ARM: Squash outstanding walks when instructions are squashed. | Ali Saidi |
2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
2012-08-28 | Clock: Rework clocks to avoid tick-to-cycle transformations | Andreas Hansson |
2012-07-09 | Port: Align port names in C++ and Python | Andreas Hansson |
2012-07-09 | Port: Move retry from port base class to Master/SlavePort | Andreas Hansson |
2012-06-08 | Timing CPU: Remove a redundant port pointer | Andreas Hansson |
2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
2012-04-14 | MEM: Separate snoops and normal memory requests/responses | Andreas Hansson |
2012-02-24 | CPU: Round-two unifying instr/data CPU ports across models | Andreas Hansson |
2012-01-31 | clang: Enable compiling gem5 using clang 2.9 and 3.0 | Koan-Sin Tan |
2012-01-17 | CPU: Moving towards a more general port across CPU models | Andreas Hansson |
2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson |
2011-07-02 | ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. | Gabe Black |
2011-07-02 | ExecContext: Get rid of the now unused read/write templated functions. | Gabe Black |
2011-04-15 | includes: sort all includes | Nathan Binkert |
2011-02-11 | SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk o... | Ali Saidi |
2011-02-11 | O3: Enhance data address translation by supporting hardware page table walkers. | Giacomo Gabrielli |
2010-11-15 | CPU: Fix bug when a split transaction is issued to a faster cache | Ali Saidi |
2010-08-13 | CPU: Add readBytes and writeBytes functions to the exec contexts. | Gabe Black |
2010-02-12 | BaseDynInst: Make the TLB translation timing instead of atomic. | Timothy M. Jones |
2009-04-08 | tlb: More fixing of unified TLB | Nathan Binkert |