| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-06-04 | types: clean up types, especially signed vs unsigned | Nathan Binkert | |
| 2009-05-26 | types: add a type for thread IDs and try to use it everywhere | Nathan Binkert | |
| 2009-05-17 | includes: sort includes again | Nathan Binkert | |
| 2009-05-17 | types: Move stuff for global types into src/base/types.hh | Nathan Binkert | |
| --HG-- rename : src/sim/host.hh => src/base/types.hh | |||
| 2009-04-20 | request: rename INST_READ to INST_FETCH. | Steve Reinhardt | |
| 2009-04-19 | Mem: Change isLlsc to isLLSC. | Gabe Black | |
| 2009-04-19 | CPUs: Make the atomic CPU support locked memory accesses. | Gabe Black | |
| 2009-04-19 | Memory: Rename LOCKED for load locked store conditional to LLSC. | Gabe Black | |
| 2009-04-19 | CPU: If the simple CPU is already idle, just return from suspendContext, ↵ | Gabe Black | |
| don't assert. | |||
| 2009-04-15 | Get rid of the Unallocated thread context state. | Steve Reinhardt | |
| Basically merge it in with Halted. Also had to get rid of a few other functions that called ThreadContext::deallocate(), including: - InOrderCPU's setThreadRescheduleCondition. - ThreadContext::exit(). This function was there to avoid terminating simulation when one thread out of a multi-thread workload exits, but we need to find a better (non-cpu-centric) way. | |||
| 2009-04-08 | tlb: More fixing of unified TLB | Nathan Binkert | |
| 2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black | |
| 2009-03-11 | cpu: fix minor endian issue with trace output | Steve Reinhardt | |
| (no functional change) | |||
| 2009-03-05 | stats: Fix all stats usages to deal with template fixes | Nathan Binkert | |
| 2009-02-26 | CPA: Add code to automatically record function symbols as CPU executes. | Ali Saidi | |
| 2009-02-25 | CPU: Don't fetch when executing a macroop. | Gabe Black | |
| If the CPL changes mid macroop, the end of the instruction might not be priveleged enough to execute the beginning. | |||
| 2009-02-25 | CPU: Implement translateTiming which defers to translateAtomic, and convert ↵ | Gabe Black | |
| the timing simple CPU to use it. | |||
| 2009-02-25 | ISA: Replace the translate functions in the TLBs with translateAtomic. | Gabe Black | |
| 2009-02-25 | CPU: Get rid of translate... functions from various interface classes. | Gabe Black | |
| 2009-02-01 | CPU: Don't always reset the micro pc on faults. Let the faults handle it. | Gabe Black | |
| 2009-02-01 | X86: Make sure the predecoder is cleared out for interrupts. | Gabe Black | |
| 2009-01-24 | cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep. | Nathan Binkert | |
| Make interrupts use the new wakeup method, and pull all of the interrupt stuff into the cpu base class so that only the wakeup code needs to be updated. I tried to make wakeup, wakeCPU, and the various other mechanisms for waking and sleeping a little more sane, but I couldn't understand why the statistics were changing the way they were. Maybe we'll try again some day. | |||
| 2009-01-06 | Tracing: Make tracing aware of macro and micro ops. | Gabe Black | |
| 2008-11-13 | CPU: Refactor read/write in the simple timing CPU. | Gabe Black | |
| 2008-11-09 | CPU: Make unaligned accesses work in the timing simple CPU. | Gabe Black | |
| 2008-11-09 | X86: Make the timing simple CPU handle variable length instructions. | Gabe Black | |
| 2008-11-02 | Add in Context IDs to the simulator. From now on, cpuId is almost never used, | Lisa Hsu | |
| the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. | |||
| 2008-11-02 | make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered | Lisa Hsu | |
| across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. | |||
| 2008-10-27 | CPU: The API change to EventWrapper did not get propagated to the entirety ↵ | Clint Smullen | |
| of TimingSimpleCPU. The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning. Signed-off By: Ali Saidi | |||
| 2008-10-21 | style: Use the correct m5 style for things relating to interrupts. | Nathan Binkert | |
| 2008-10-20 | O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. ↵ | Ali Saidi | |
| Removing hwrei causes the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change. | |||
| 2008-10-12 | CPU: Explain why some code is commented out. | Gabe Black | |
| 2008-10-12 | X86: Don't fetch in the simple CPU if you're in the ROM. | Gabe Black | |
| 2008-10-12 | CPU: Make the highest order bit in the micro pc determine if it's ↵ | Gabe Black | |
| combinational or from the ROM. | |||
| 2008-10-12 | Turn Interrupts objects into SimObjects. Also, move local APIC state into ↵ | Gabe Black | |
| x86's Interrupts object. | |||
| 2008-10-11 | CPU: Eliminate the simPalCheck funciton. | Gabe Black | |
| 2008-10-11 | CPU: Eliminate the hwrei function. | Gabe Black | |
| 2008-10-09 | eventq: convert all usage of events to use the new API. | Nathan Binkert | |
| For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. | |||
| 2008-09-10 | style: Remove non-leading tabs everywhere they shouldn't be. Developers ↵ | Ali Saidi | |
| should configure their editors to not insert tabs | |||
| 2008-08-19 | CPU: Get rid of two more duplicated CPU params. | Gabe Black | |
| 2008-08-18 | Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was ↵ | Richard Strong | |
| done to be consistent with its python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused problems for intialization of the interval value. If a child class's profile value was defined, the parent BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the multiple redifitions of profile in the child CPU classes. | |||
| 2008-08-11 | params: Convert the CPU objects to use the auto generated param structs. | Nathan Binkert | |
| A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. | |||
| 2008-07-15 | Use ReadResp instead of LoadLockedResp for LoadLockedReq responses. | Steve Reinhardt | |
| 2008-07-01 | Make the cached virtPort have a thread context so it can do everything that ↵ | Ali Saidi | |
| a newly created one can. | |||
| 2008-07-01 | After a checkpoint (and thus a stats reset), the ↵ | Ali Saidi | |
| not_idle_fraction/notIdleFraction statistic is really wrong. The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing with Port::Status, but _status seems a bit strage too. | |||
| 2008-06-18 | AtomicSimpleCPU: Separate data stalls from instruction stalls. | Nathan Binkert | |
| Separate simulation of icache stalls and dat stalls. | |||
| 2008-06-12 | CPU: Make the simple cpu trace data for loads/stores. | Gabe Black | |
| 2008-02-26 | TLB: Make a TLB base class and put a virtual demapPage function in it. | Gabe Black | |
| --HG-- extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f | |||
| 2008-02-14 | CPU: move the PC Events code to a place where the code won't be executed ↵ | Ali Saidi | |
| multiple times if an instruction faults. --HG-- extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68 | |||
| 2008-02-06 | Make the Event::description() a const function | Stephen Hines | |
| --HG-- extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0 | |||
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |