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path: root/src/cpu/simple
AgeCommit message (Expand)Author
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-11-14arm: Fixes based on UBSan and static analysisAndreas Hansson
2014-11-12arm: Fix timing wakeup with LLSCAli Saidi
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-10-16cpu: Probe points for basic PMU statsAndreas Sandberg
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-20cpu: Remove unused deallocateContext callsMitch Hayenga
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-20cpu: use probes infrastructure to do simpoint profilingDam Sunwoo
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-05-09cpu: add more instruction mix statisticsCurtis Dunham
2014-02-09cpu: simple: Add support for using branch predictorsAndreas Sandberg
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2014-01-24cpu: remove faulty simpoint basic block inst count assertionDam Sunwoo
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu: rename *_DepTag constants to *_Reg_BaseSteve Reinhardt
2013-08-20cpu: Fix timing CPU isDrained comment formattingAndreas Hansson
2013-08-19cpu: Accurately count idle cycles for simple cpuLena Olson
2013-08-19cpu: Fix timing CPU drain checkAndreas Hansson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-05-30cpu: Make hash struct instead of class to please clangAndreas Hansson
2013-04-22sim: separate nextCycle() and clockEdge() in clockedObjectsDam Sunwoo
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-01-12base simple cpu: removes commented out code about cache opsNilay Vaish
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg
2013-01-07cpu: Make sure that a drained atomic CPU isn't executing ucodeAndreas Sandberg
2013-01-07cpu: Make sure that a drained timing CPU isn't executing ucodeAndreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Correctly call parent on switchOut() and takeOverFrom()Andreas Sandberg
2013-01-07cpu: Check that the memory system is in the correct modeAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
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