| Age | Commit message (Expand) | Author |
|---|
| 2016-08-15 | cpu, arch: fix the type used for the request flags | Nikos Nikoleris |
| 2016-06-06 | pwr: Low-power idle power state for idle CPUs | David Guillen Fandos |
| 2016-04-07 | mem: Remove threadId from memory request class | Mitch Hayenga |
| 2016-04-06 | Revert power patch sets with unexpected interactions | Andreas Sandberg |
| 2016-04-05 | mem: Remove threadId from memory request class | Mitch Hayenga |
| 2014-12-09 | power: Low-power idle power state for idle CPUs | Akash Bagdia |
| 2015-11-27 | base: Add support for changing output directories | Andreas Sandberg |
| 2015-07-19 | cpu: Fix LLSC atomic CPU wakeup | Krishnendra Nathella |
| 2016-02-10 | mem: Deduce if cache should forward snoops | Andreas Hansson |
| 2016-02-06 | style: fix missing spaces in control statements | Steve Reinhardt |
| 2016-02-06 | style: remove trailing whitespace | Steve Reinhardt |
| 2016-01-17 | cpu. arch: add initiateMemRead() to ExecContext interface | Steve Reinhardt |
| 2015-10-12 | misc: Add explicit overrides and fix other clang >= 3.5 issues | Andreas Hansson |
| 2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
| 2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
| 2015-09-30 | isa,cpu: Add support for FS SMT Interrupts | Mitch Hayenga |
| 2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
| 2015-09-30 | config,cpu: Add SMT support to Atomic and Timing CPUs | Mitch Hayenga |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-04-13 | cpu: re-organizes the branch predictor structure. | Dibakar Gope |
| 2015-04-03 | cpu: fix system total instructions accounting | Nikos Nikoleris |
| 2015-03-23 | mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW | Steve Reinhardt |
| 2015-02-11 | mem: restructure Packet cmd initialization a bit more | Steve Reinhardt |
| 2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
| 2015-02-16 | arch: Make readMiscRegNoEffect const throughout | Andreas Hansson |
| 2015-02-03 | cpu: Ensure timing CPU sinks response before sending new request | Andreas Hansson |
| 2015-01-25 | sim: Clean up InstRecord | Ali Saidi |
| 2015-01-25 | cpu: Remove all notion that we know when the cpu is misspeculating. | Ali Saidi |
| 2015-01-22 | mem: Clean up Request initialisation | Andreas Hansson |
| 2015-01-20 | cpu: commit probe notification on every microop or macroop | Nikos Nikoleris |
| 2014-12-05 | cpu: Only check for PC events on instruction boundaries. | Gabe Black |
| 2014-12-02 | mem: Assume all dynamic packet data is array allocated | Andreas Hansson |
| 2014-12-02 | mem: Add const getters for write packet data | Andreas Hansson |
| 2014-11-14 | arm: Fixes based on UBSan and static analysis | Andreas Hansson |
| 2014-11-12 | arm: Fix timing wakeup with LLSC | Ali Saidi |
| 2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
| 2014-10-16 | cpu: Probe points for basic PMU stats | Andreas Sandberg |
| 2014-09-27 | arch: Use const StaticInstPtr references where possible | Andreas Hansson |
| 2014-09-20 | cpu: Remove unused deallocateContext calls | Mitch Hayenga |
| 2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
| 2014-09-20 | cpu: use probes infrastructure to do simpoint profiling | Dam Sunwoo |
| 2014-09-19 | arch: Pass faults by const reference where possible | Andreas Hansson |
| 2014-05-13 | mem: Refactor assignment of Packet types | Curtis Dunham |
| 2014-09-03 | arch, cpu: Factor out the ExecContext into a proper base class | Andreas Sandberg |
| 2014-05-09 | cpu: add more instruction mix statistics | Curtis Dunham |
| 2014-02-09 | cpu: simple: Add support for using branch predictors | Andreas Sandberg |
| 2014-01-24 | cpu: Add support for instructions that zero cache lines. | Ali Saidi |
