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--HG--
extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6
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--HG--
rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc
rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh
rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc
rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh
rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh
rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc
rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh
extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966
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--HG--
extra : convert_revision : b3f956af92cb98b4945aebc8aece1dffcabdf15c
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/SConscript:
SCCS merged
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extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
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src/cpu/base.cc:
Move clock phase drift code to the base CPU so that any CPU model can use it.
src/cpu/base.hh:
Added two functions to help get the next cycle the CPU should be scheduled.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Use the function now in BaseCPU.
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extra : convert_revision : 444494b66ffc85fc473c23f57683c5f9458ad80c
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are in PAL mode, however.
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extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
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records when interrupts are requested, and returns an interrupt to execute if the
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extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
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src/arch/alpha/utility.hh:
For now makeExtMI will be specific to the ISA.
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extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
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file functions to not take faults
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extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
Hand merge.
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extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
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for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
No need for mem parameter any more.
src/cpu/checker/cpu.cc:
Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
Remove memory parameter.
--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
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src/cpu/simple/atomic.hh:
Port now takes in the MemObject that owns it.
src/cpu/simple/timing.hh:
Port now takes in MemObject that owns it.
src/dev/io_device.cc:
src/mem/bus.hh:
Ports now take in the MemObject that owns it.
src/mem/cache/base_cache.cc:
Ports now take in the MemObject that own it.
src/mem/port.hh:
src/mem/tport.hh:
Ports now optionally take in the MemObject that owns it.
--HG--
extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
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functions.
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extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
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more neutral names.
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extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
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src/cpu/simple/base.cc:
Make a microcoded op start at the current micropc, rather than starting at 0.
src/cpu/thread_state.cc:
Serialize the microPC and nextMicroPC
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extra : convert_revision : 5302215f17312ecef3ff4c6548acb05297ee4ff6
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--HG--
extra : convert_revision : aad1ee04ade9f4394c9ef0386f23d6f2ca373412
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--HG--
extra : convert_revision : 4762b8ab46ac755726cc658a378c2cf5b2061dc3
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--HG--
extra : convert_revision : 8e46929ed7da5dae6888f773de4e1ecc9b249fe0
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--HG--
extra : convert_revision : b2d505de51fc5fcae5177b2a13140729474e249e
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--HG--
extra : convert_revision : 51572523190a886fd0ff64817edc88e260c5fa9d
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
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--HG--
extra : convert_revision : 3c165af27ea0e6c7f2a17819c1717d8900f54cc1
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--HG--
extra : convert_revision : a8ddc6b213b1a1b0d9c5cd194b88ac0c6bfb2a21
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
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--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
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and call it packet_access.hh and fix the #includes so
things compile right.
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extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
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Still a bug in atomic uni-coherence in FS.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
Only deallocate once
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extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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extra : convert_revision : 898976bbd322e55bc234035456df8090c6dcf72d
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src/arch/sparc/isa/formats/blockmem.isa:
Several small and medium bug fixes.
src/cpu/simple/base.cc:
Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug.
src/cpu/thread_state.cc:
Made sure the microPC and nextMicroPC are initialized properly.
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extra : convert_revision : a0fc8aa18d1ade916f17c557181a793c6108a8af
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--HG--
extra : convert_revision : 51df0454085e13df023efd8a0c0a12f9756c4690
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
src/cpu/simple/timing.cc:
hand merge
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extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
--HG--
extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
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changes so that when you come out of resume, you only assert if you're really wrong.
src/cpu/simple/atomic.cc:
memory mode assertion change so that it only goes off if it's supposed to.
src/cpu/simple/timing.cc:
some drain changes (kevin's) and some changes to memoryMode assertions so that they don't go off when they're not supposed to.
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extra : convert_revision : 007d8610f097e08f01367b905ada49f93cf37ca3
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.
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extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
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src/cpu/o3/cpu.cc:
Fix up caches plus sampling switch over.
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extra : convert_revision : 49d0c16d4c5e8d5ba83749d568a4efe3b42e3a97
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--HG--
extra : convert_revision : 2a1fba141e409ee1d7a0b69b5b21d236e3d4ce68
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 77b06379a520dd91f124c0a543e30ec3a9cd1452
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right now unserializing breaks an assert since CPU status is not saved. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.
src/cpu/simple/atomic.cc:
add in serialization of AtomicSimpleCPU _status. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.
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extra : convert_revision : 7000f660aecea6fef712bf81853d9a7b90d625ee
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If the cpu needs to update any state when it gets a functional write (LSQ??)
then that code needs to be written.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
CPU's can recieve functional accesses, they need to determine if they need to do anything with them.
src/mem/bus.cc:
src/mem/bus.hh:
Make the fuctional path do the correct tye of snoop
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extra : convert_revision : 70d09f954b907a8aa9b8137579cd2b06e02ae2ff
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--HG--
extra : convert_revision : f22ce3221d270ecf8631d3dcaed05753accd5461
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and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
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extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
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--HG--
extra : convert_revision : 765283ae54d2d6b5885ea44c6c1813d4bcf18488
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src/cpu/simple/timing.cc:
Record numCycles stat properly.
src/cpu/simple/timing.hh:
Extra variable to help record numCycles stat.
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extra : convert_revision : 343311902831820264878aad41dc619999726b6b
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middle of another section and messed up unserializing.
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extra : convert_revision : 7af15fdc9e8d203b26840a2eb5fef511b6a2b21d
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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extra : convert_revision : f7d41fc21c7eeca6edde0b01f2e8844e3e19c51a
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision : 1010a4ee8e1abec0e8290637feee523ca9ef9a9b
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--HG--
extra : convert_revision : 793ca7d6af1deedf6b1fb4676288b11114f583a6
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
src/cpu/ozone/cpu_impl.hh:
Hand merged
--HG--
extra : convert_revision : f8a5b0205bcb78c8f5e109f456fe7bca80a7abac
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