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path: root/src/cpu/simple
AgeCommit message (Expand)Author
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
2007-11-08TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.Ali Saidi
2007-11-08AtomicSimpleCPU: Refactor resume() code to have a cleaner control path.Ali Saidi
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one f...Ali Saidi
2007-10-22CPU: Add functions to the "ExecContext"s that translate a given address.Gabe Black
2007-10-18CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.Ali Saidi
2007-10-02Merge with head.Gabe Black
2007-10-02Predecoder: Clear out predecoder state on an ITLB fault.Gabe Black
2007-10-02CPU: Make the cpus check the pc event queues in SE mode.Gabe Black
2007-10-01CPU: fix sparc_fs booting with SimpleTimingCPU.Ali Saidi
2007-09-28Update stats for quiesced cyclesAli Saidi
2007-09-28Rename cycles() function to ticks()Ali Saidi
2007-09-28Update statistics to use cycles properly instead of ticksAli Saidi
2007-09-24X86: Get X86_FS to compile.Gabe Black
2007-08-26Merge with headGabe Black
2007-08-26Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.Gabe Black
2007-08-26Simple CPU: Added code that will split requests that cross block boundaries i...Gabe Black
2007-08-26Simple CPU: Make sure only instructions which complete without faulting are c...Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-08-08Added fastmem option.Vincentius Robby
2007-08-07X86: Make a microcode branch microop.Gabe Black
2007-08-04SimpleCPU: Add some DPRINTFsNathan Binkert
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-07-28AtomicSimpleCPU: fix inadvertent loss of endian conversion on read.Steve Reinhardt
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-07-02Couple more minor bug fixes for FS timing mode.Steve Reinhardt
2007-07-02Fix a couple LL/SC bugs that only affected timing mode.Steve Reinhardt
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-22mips import pt. 1Korey Sewell
2007-06-19Make branches work by repopulating the predecoder every time through. This is...Gabe Black
2007-06-18fix bug in timing cpu. getTime() is the time the requset was created, not the...Ali Saidi
2007-06-14Modified instruction decode method.Vincentius Robby
2007-06-13Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "more...Gabe Black
2007-06-12Make microOp vs microop and macroOp vs macroop capitilization consistent.Gabe Black
2007-06-04don't be so aggressive with the tracing on #ifAli Saidi
2007-06-02Don't mask the pc because the Alpha predecoder needs it to set the PAL mode b...Gabe Black
2007-06-01cast sizeof(MachInst) to Addr before generating a maskAli Saidi
2007-05-31Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-05-31Assign traceData to be NULL at BaseSimpleCPU constructor.Vincentius Robby
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
2007-05-25Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-20Add new EventWrapper constructor that takes a Tick valueSteve Reinhardt
2007-05-18Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-05-18Changes to make simple cpu handle pcs appropriately for x86Gabe Black
2007-05-07the bridge never returns false when recvTiming() is called on its ports now, ...Ali Saidi
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