| Age | Commit message (Expand) | Author |
|---|
| 2014-01-24 | cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo... | Ali Saidi |
| 2014-01-24 | mem: per-thread cache occupancy and per-block ages | Dam Sunwoo |
| 2014-01-24 | mem: track per-request latencies and access depths in the cache hierarchy | Matt Horsnell |
| 2014-01-24 | cpu: remove faulty simpoint basic block inst count assertion | Dam Sunwoo |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2013-10-15 | cpu: rename *_DepTag constants to *_Reg_Base | Steve Reinhardt |
| 2013-08-20 | cpu: Fix timing CPU isDrained comment formatting | Andreas Hansson |
| 2013-08-19 | cpu: Accurately count idle cycles for simple cpu | Lena Olson |
| 2013-08-19 | cpu: Fix timing CPU drain check | Andreas Hansson |
| 2013-07-18 | mem: Set the cache line size on a system level | Andreas Hansson |
| 2013-05-30 | cpu: Make hash struct instead of class to please clang | Andreas Hansson |
| 2013-04-22 | sim: separate nextCycle() and clockEdge() in clockedObjects | Dam Sunwoo |
| 2013-04-22 | cpu: generate SimPoint basic block vector profiles | Dam Sunwoo |
| 2013-03-26 | cpu: Remove CpuPort and use MasterPort in the CPU classes | Andreas Hansson |
| 2013-02-15 | sim: Add a system-global option to bypass caches | Andreas Sandberg |
| 2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
| 2013-02-15 | cpu: Add CPU metadata om the Python classes | Andreas Sandberg |
| 2013-01-12 | base simple cpu: removes commented out code about cache ops | Nilay Vaish |
| 2013-01-12 | x86: Changes to decoder, corrects 9376 | Nilay Vaish |
| 2013-01-07 | cpu: Unify the serialization code for all of the CPU models | Andreas Sandberg |
| 2013-01-07 | cpu: Make sure that a drained atomic CPU isn't executing ucode | Andreas Sandberg |
| 2013-01-07 | cpu: Make sure that a drained timing CPU isn't executing ucode | Andreas Sandberg |
| 2013-01-07 | cpu: Rename defer_registration->switched_out | Andreas Sandberg |
| 2013-01-07 | cpu: Correctly call parent on switchOut() and takeOverFrom() | Andreas Sandberg |
| 2013-01-07 | cpu: Check that the memory system is in the correct mode | Andreas Sandberg |
| 2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg |
| 2013-01-04 | Decoder: Remove the thread context get/set from the decoder. | Gabe Black |
| 2012-11-02 | sim: Move the draining interface into a separate base class | Andreas Sandberg |
| 2012-11-02 | sim: Include object header files in SWIG interfaces | Andreas Sandberg |
| 2012-09-25 | ARM: Squash outstanding walks when instructions are squashed. | Ali Saidi |
| 2012-09-19 | AddrRange: Transition from Range<T> to AddrRange | Andreas Hansson |
| 2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
| 2012-08-28 | Clock: Rework clocks to avoid tick-to-cycle transformations | Andreas Hansson |
| 2012-08-22 | Packet: Remove NACKs from packet and its use in endpoints | Andreas Hansson |
| 2012-08-15 | O3,ARM: fix some problems with drain/switchout functionality and add Drain DP... | Anthony Gutierrez |
| 2012-07-09 | Port: Align port names in C++ and Python | Andreas Hansson |
| 2012-07-09 | Port: Move retry from port base class to Master/SlavePort | Andreas Hansson |
| 2012-06-08 | Timing CPU: Remove a redundant port pointer | Andreas Hansson |
| 2012-06-05 | cpu: Don't init simple and inorder CPUs if they are defered. | Anthony Gutierrez |
| 2012-05-26 | CPU: Merge the predecoder and decoder. | Gabe Black |
| 2012-05-25 | Decode: Make the Decoder class defined per ISA. | Gabe Black |
| 2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
| 2012-04-15 | CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class. | Gabe Black |
| 2012-04-14 | MEM: Remove the Broadcast destination from the packet | Andreas Hansson |
| 2012-04-14 | MEM: Separate snoops and normal memory requests/responses | Andreas Hansson |
| 2012-04-06 | MEM: Enable multiple distributed generalized memories | Andreas Hansson |
| 2012-04-03 | Atomic: Remove the physmem_port and access memory directly | Andreas Hansson |
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
| 2012-03-30 | CPU: Unify initMemProxies across CPUs and simulation modes | Andreas Hansson |
| 2012-03-09 | CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable | Geoffrey Blake |
