| Age | Commit message (Expand) | Author |
|---|
| 2012-11-02 | sim: Move the draining interface into a separate base class | Andreas Sandberg |
| 2012-11-02 | sim: Include object header files in SWIG interfaces | Andreas Sandberg |
| 2012-09-25 | ARM: Squash outstanding walks when instructions are squashed. | Ali Saidi |
| 2012-09-19 | AddrRange: Transition from Range<T> to AddrRange | Andreas Hansson |
| 2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
| 2012-08-28 | Clock: Rework clocks to avoid tick-to-cycle transformations | Andreas Hansson |
| 2012-08-22 | Packet: Remove NACKs from packet and its use in endpoints | Andreas Hansson |
| 2012-08-15 | O3,ARM: fix some problems with drain/switchout functionality and add Drain DP... | Anthony Gutierrez |
| 2012-07-09 | Port: Align port names in C++ and Python | Andreas Hansson |
| 2012-07-09 | Port: Move retry from port base class to Master/SlavePort | Andreas Hansson |
| 2012-06-08 | Timing CPU: Remove a redundant port pointer | Andreas Hansson |
| 2012-06-05 | cpu: Don't init simple and inorder CPUs if they are defered. | Anthony Gutierrez |
| 2012-05-26 | CPU: Merge the predecoder and decoder. | Gabe Black |
| 2012-05-25 | Decode: Make the Decoder class defined per ISA. | Gabe Black |
| 2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
| 2012-04-15 | CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class. | Gabe Black |
| 2012-04-14 | MEM: Remove the Broadcast destination from the packet | Andreas Hansson |
| 2012-04-14 | MEM: Separate snoops and normal memory requests/responses | Andreas Hansson |
| 2012-04-06 | MEM: Enable multiple distributed generalized memories | Andreas Hansson |
| 2012-04-03 | Atomic: Remove the physmem_port and access memory directly | Andreas Hansson |
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
| 2012-03-30 | CPU: Unify initMemProxies across CPUs and simulation modes | Andreas Hansson |
| 2012-03-09 | CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable | Geoffrey Blake |
| 2012-02-24 | CPU: Round-two unifying instr/data CPU ports across models | Andreas Hansson |
| 2012-02-13 | MEM: Introduce the master/slave port roles in the Python classes | Andreas Hansson |
| 2012-02-12 | cpu: add separate stats for insts/ops both globally and per cpu model | Anthony Gutierrez |
| 2012-02-12 | mem: Add a master ID to each request object. | Ali Saidi |
| 2012-02-10 | SE/FS: Record the system pointer all the time for the simple CPU. | Gabe Black |
| 2012-02-07 | Faults: Turn off arch/faults.hh | Gabe Black |
| 2012-01-31 | Merge with head, hopefully the last time for this batch. | Gabe Black |
| 2012-01-31 | clang: Enable compiling gem5 using clang 2.9 and 3.0 | Koan-Sin Tan |
| 2012-01-31 | CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 | Geoffrey Blake |
| 2012-01-29 | Implement Ali's review feedback. | Gabe Black |
| 2012-01-28 | Merge with the main repo. | Gabe Black |
| 2012-01-17 | MEM: Separate queries for snooping and address ranges | Andreas Hansson |
| 2012-01-17 | MEM: Simplify ports by removing EventManager | Andreas Hansson |
| 2012-01-17 | CPU: Moving towards a more general port across CPU models | Andreas Hansson |
| 2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson |
| 2011-11-18 | SE/FS: Get rid of FULL_SYSTEM in the CPU directory. | Gabe Black |
| 2011-11-01 | SE/FS: Get rid of uses of FULL_SYSTEM in Alpha. | Gabe Black |
| 2011-11-01 | SE/FS: Expose the same methods on the CPUs in SE and FS modes. | Gabe Black |
| 2011-09-19 | Syscall: Make the syscall function available in both SE and FS modes. | Gabe Black |
| 2011-09-09 | Decode: Pull instruction decoding out of the StaticInst class into its own. | Gabe Black |
| 2011-08-07 | Translation: Use a pointer type as the template argument. | Gabe Black |
| 2011-07-02 | ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. | Gabe Black |
| 2011-07-02 | ExecContext: Get rid of the now unused read/write templated functions. | Gabe Black |
| 2011-06-02 | scons: rename TraceFlags to DebugFlags | Nathan Binkert |
| 2011-05-04 | CPU: Add some useful debug message to the timing simple cpu. | Ali Saidi |
| 2011-05-04 | CPU: Fix a case where timing simple cpu faults can nest. | Ali Saidi |
| 2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert |
