Age | Commit message (Collapse) | Author |
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Separate simulation of icache stalls and dat stalls.
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multiple times if an instruction faults.
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to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
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"setShadowSet", "CacheOp"
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file with them all.
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into multiple memory access.
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counted.
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Lets CPU accesses to physical memory bypass Bus.
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Also some touch up for ruflag.
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These need to be refined a little still and given parameters.
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creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
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src/cpu/simple/timing.cc:
Fix another SC problem.
src/mem/cache/cache_impl.hh:
Forgot to call makeTimingResponse() on uncached timing responses.
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src/cpu/simple/timing.cc:
Fix swap/stq_c command bug.
src/mem/packet.cc:
Fix incorrect LoadLockedReq command response field.
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(they function as adjectives not nouns)
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now encoded in cmd field.
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src/arch/mips/SConscript:
"mips import pt.1".
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is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.
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the time it was repsonded to. In timing mode the
time it was responded to is curTick. Doesn't change the results, but it does make implementation of nextCycle() more difficult
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Make code compatible with new decode method.
src/arch/alpha/remote_gdb.cc:
src/cpu/base_dyn_inst_impl.hh:
src/cpu/exetrace.cc:
src/cpu/simple/base.cc:
Make code compatible with new decode method.
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
Modified instruction decode method.
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