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AgeCommit message (Expand)Author
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory instru...Min Kyu Jeong
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
2010-08-13Merge with head.Gabe Black
2010-08-13CPU: Add readBytes and writeBytes functions to the exec contexts.Gabe Black
2010-08-13CPU: Tidy up endianness handling for mmapped "IPR"s.Gabe Black
2010-08-12TimingSimpleCPU: fix NO_ACCESS memory op handlingJoel Hestness
2010-06-14stats: get rid of the never-really-used event stuffNathan Binkert
2010-06-03Minor remote GDB cleanup.Steve Reinhardt
2010-06-02ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.Gabe Black
2010-06-02CPU: Reset fetch offset after a exceptionAli Saidi
2010-06-02ARM: Make the predecoder handle Thumb instructions.Gabe Black
2010-03-23cpu: get rid of uncached access "events"Steve Reinhardt
2010-03-23cpu: fix exec tracing memory corruption bugSteve Reinhardt
2010-03-21TimingSimpleCPU: Fixed uncacacheable request read bugBrad Beckmann
2010-02-26cpu_models: get rid of cpu_models.py and move the stuff into SConsNathan Binkert
2010-02-12BaseDynInst: Make the TLB translation timing instead of atomic.Timothy M. Jones
2009-11-18m5: Fixed bug in atomic cpu destructorBrad Beckmann
2009-11-10Mem: Eliminate the NO_FAULT request flag.Gabe Black
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2009-08-23Atomic CPU: Respect the NO_ACCESS request flag.Gabe Black
2009-08-01Fix setting of INST_FETCH flag for O3 CPU.Steve Reinhardt
2009-07-08Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.Gabe Black
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
2009-04-20request: rename INST_READ to INST_FETCH.Steve Reinhardt
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19CPUs: Make the atomic CPU support locked memory accesses.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-04-19CPU: If the simple CPU is already idle, just return from suspendContext, don'...Gabe Black
2009-04-15Get rid of the Unallocated thread context state.Steve Reinhardt
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-03-11cpu: fix minor endian issue with trace outputSteve Reinhardt
2009-03-05stats: Fix all stats usages to deal with template fixesNathan Binkert
2009-02-26CPA: Add code to automatically record function symbols as CPU executes.Ali Saidi
2009-02-25CPU: Don't fetch when executing a macroop.Gabe Black
2009-02-25CPU: Implement translateTiming which defers to translateAtomic, and convert t...Gabe Black
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2009-02-01CPU: Don't always reset the micro pc on faults. Let the faults handle it.Gabe Black
2009-02-01X86: Make sure the predecoder is cleared out for interrupts.Gabe Black
2009-01-24cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.Nathan Binkert
2009-01-06Tracing: Make tracing aware of macro and micro ops.Gabe Black
2008-11-13CPU: Refactor read/write in the simple timing CPU.Gabe Black
2008-11-09CPU: Make unaligned accesses work in the timing simple CPU.Gabe Black
2008-11-09X86: Make the timing simple CPU handle variable length instructions.Gabe Black
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