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path: root/src/cpu/simple
AgeCommit message (Expand)Author
2008-07-15Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.Steve Reinhardt
2008-07-01Make the cached virtPort have a thread context so it can do everything that a...Ali Saidi
2008-07-01After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFra...Ali Saidi
2008-06-18AtomicSimpleCPU: Separate data stalls from instruction stalls.Nathan Binkert
2008-06-12CPU: Make the simple cpu trace data for loads/stores.Gabe Black
2008-02-26TLB: Make a TLB base class and put a virtual demapPage function in it.Gabe Black
2008-02-14CPU: move the PC Events code to a place where the code won't be executed mult...Ali Saidi
2008-02-06Make the Event::description() a const functionStephen Hines
2008-02-05Add base ARM code to M5Stephen Hines
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
2007-12-16CPU: Update where the simple cpus read their cpu id from the thread context t...Ali Saidi
2007-11-21imported patch pagewalker.patchGabe Black
2007-11-20Simple CPU fix simple mistake in translateDataWriteAddr.Gabe Black
2007-11-15Get MIPS simple regression working. Take out unecessary functions "setShadowS...Korey Sewell
2007-11-15branch mergeKorey Sewell
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
2007-11-12X86: Work on the page table walker, TLB, and related faults.Gabe Black
2007-11-12X86: Implement a page table walker.Gabe Black
2007-11-08TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.Ali Saidi
2007-11-08AtomicSimpleCPU: Refactor resume() code to have a cleaner control path.Ali Saidi
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one f...Ali Saidi
2007-10-22CPU: Add functions to the "ExecContext"s that translate a given address.Gabe Black
2007-10-18CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.Ali Saidi
2007-10-02Merge with head.Gabe Black
2007-10-02Predecoder: Clear out predecoder state on an ITLB fault.Gabe Black
2007-10-02CPU: Make the cpus check the pc event queues in SE mode.Gabe Black
2007-10-01CPU: fix sparc_fs booting with SimpleTimingCPU.Ali Saidi
2007-09-28Update stats for quiesced cyclesAli Saidi
2007-09-28Rename cycles() function to ticks()Ali Saidi
2007-09-28Update statistics to use cycles properly instead of ticksAli Saidi
2007-09-24X86: Get X86_FS to compile.Gabe Black
2007-08-26Merge with headGabe Black
2007-08-26Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.Gabe Black
2007-08-26Simple CPU: Added code that will split requests that cross block boundaries i...Gabe Black
2007-08-26Simple CPU: Make sure only instructions which complete without faulting are c...Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-08-08Added fastmem option.Vincentius Robby
2007-08-07X86: Make a microcode branch microop.Gabe Black
2007-08-04SimpleCPU: Add some DPRINTFsNathan Binkert
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-07-28AtomicSimpleCPU: fix inadvertent loss of endian conversion on read.Steve Reinhardt
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-07-02Couple more minor bug fixes for FS timing mode.Steve Reinhardt
2007-07-02Fix a couple LL/SC bugs that only affected timing mode.Steve Reinhardt
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-22mips import pt. 1Korey Sewell
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