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2007-11-15branch mergeKorey Sewell
--HG-- extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
--HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
2007-11-12X86: Work on the page table walker, TLB, and related faults.Gabe Black
--HG-- extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
2007-11-12X86: Implement a page table walker.Gabe Black
--HG-- extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
2007-11-08TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.Ali Saidi
--HG-- extra : convert_revision : a305cf9dcaca5ed3b97499a5e24c511f4416125a
2007-11-08AtomicSimpleCPU: Refactor resume() code to have a cleaner control path.Ali Saidi
--HG-- extra : convert_revision : f27bb96850e7fb0252fb1f47c3d0860705c32884
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one ↵Ali Saidi
file with them all. --HG-- extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-10-22CPU: Add functions to the "ExecContext"s that translate a given address.Gabe Black
--HG-- extra : convert_revision : 7d898c6b6b13094fd05326eaa0b095a3ab132397
2007-10-18CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.Ali Saidi
--HG-- extra : convert_revision : 6d025764682181b1f67df3b1d8d1d59099136df7
2007-10-02Merge with head.Gabe Black
--HG-- extra : convert_revision : 1aa0e4569a7c10e6a395c2c951ac29275b5bcf59
2007-10-02Predecoder: Clear out predecoder state on an ITLB fault.Gabe Black
--HG-- extra : convert_revision : 68f8ff778dbd28ade5070edf5a7d662e7bf0045a
2007-10-02CPU: Make the cpus check the pc event queues in SE mode.Gabe Black
--HG-- extra : convert_revision : 9dc4ea136c3c3f87a73d55e91bc4aae4eba70464
2007-10-01CPU: fix sparc_fs booting with SimpleTimingCPU.Ali Saidi
--HG-- extra : convert_revision : 3d95f6daa7f0e8e376d1a880f64c056619263885
2007-09-28Update stats for quiesced cyclesAli Saidi
--HG-- extra : convert_revision : 703ba58f156c9f2677b020f05d36bc1e3ae0b9e5
2007-09-28Rename cycles() function to ticks()Ali Saidi
--HG-- extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
2007-09-28Update statistics to use cycles properly instead of ticksAli Saidi
--HG-- extra : convert_revision : 62911280b631ef24720f9ce701d1c19a9b8a9784
2007-09-24X86: Get X86_FS to compile.Gabe Black
--HG-- extra : convert_revision : fb973bcf13648876d5691231845dd47a2be50f01
2007-08-26Merge with headGabe Black
--HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
2007-08-26Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.Gabe Black
--HG-- extra : convert_revision : 4446d9544d58bdadbd24d8322bb63016a32aa2b8
2007-08-26Simple CPU: Added code that will split requests that cross block boundaries ↵Gabe Black
into multiple memory access. --HG-- extra : convert_revision : 600f79f32ef30a6e1db951503bcfe8cd332858d1
2007-08-26Simple CPU: Make sure only instructions which complete without faulting are ↵Gabe Black
counted. --HG-- extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
2007-08-08Added fastmem option.Vincentius Robby
Lets CPU accesses to physical memory bypass Bus. --HG-- extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
2007-08-07X86: Make a microcode branch microop.Gabe Black
Also some touch up for ruflag. --HG-- extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
2007-08-04SimpleCPU: Add some DPRINTFsNathan Binkert
--HG-- extra : convert_revision : 5fdd5a9595c3e5d6ce5f9e8c9af0a8e6c857551c
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
--HG-- extra : convert_revision : d00b7b09c7f19bc0e37b385ef7c124f69c0e917f
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-28AtomicSimpleCPU: fix inadvertent loss of endian conversion on read.Steve Reinhardt
--HG-- extra : convert_revision : 367bf2431bf4f4eb7c4d5723816e5db6f7233aed
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
--HG-- extra : convert_revision : e06a950964286604274fba81dcca362d75847233
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-02Couple more minor bug fixes for FS timing mode.Steve Reinhardt
src/cpu/simple/timing.cc: Fix another SC problem. src/mem/cache/cache_impl.hh: Forgot to call makeTimingResponse() on uncached timing responses. --HG-- extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209
2007-07-02Fix a couple LL/SC bugs that only affected timing mode.Steve Reinhardt
src/cpu/simple/timing.cc: Fix swap/stq_c command bug. src/mem/packet.cc: Fix incorrect LoadLockedReq command response field. --HG-- extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
--HG-- extra : convert_revision : ab78d9d1d88c3698edfd653d71c8882e1272b781
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
(they function as adjectives not nouns) --HG-- extra : convert_revision : 6506474ff3356ae8c80ed276c3608d8a4680bfdb
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
now encoded in cmd field. --HG-- extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
2007-06-22mips import pt. 1Korey Sewell
src/arch/mips/SConscript: "mips import pt.1". --HG-- extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
2007-06-19Make branches work by repopulating the predecoder every time through. This ↵Gabe Black
is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though. --HG-- extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
2007-06-18fix bug in timing cpu. getTime() is the time the requset was created, not ↵Ali Saidi
the time it was repsonded to. In timing mode the time it was responded to is curTick. Doesn't change the results, but it does make implementation of nextCycle() more difficult --HG-- extra : convert_revision : 67ed6261a5451d17d96d5df45992590acc353afc
2007-06-14Modified instruction decode method.Vincentius Robby
Make code compatible with new decode method. src/arch/alpha/remote_gdb.cc: src/cpu/base_dyn_inst_impl.hh: src/cpu/exetrace.cc: src/cpu/simple/base.cc: Make code compatible with new decode method. src/cpu/static_inst.cc: src/cpu/static_inst.hh: Modified instruction decode method. --HG-- extra : convert_revision : a9a6d3a16fff59bc95d0606ea344bd57e71b8d0a
2007-06-13Seperate the pc-pc and the pc of the incoming bytes, and get rid of the ↵Gabe Black
"moreBytes" which just takes a MachInst. src/arch/x86/predecoder.cc: Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes. --HG-- extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0
2007-06-12Make microOp vs microop and macroOp vs macroop capitilization consistent.Gabe Black
src/arch/x86/isa/macroop.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code. src/arch/x86/isa/microops/base.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation. --HG-- extra : convert_revision : 6f4bacfa334c42732c845f9a7f211cbefc73f96f
2007-06-04don't be so aggressive with the tracing on #ifAli Saidi
--HG-- extra : convert_revision : 8ee88bff8010dcb7a412f6a6b49d40fad1c0bb68
2007-06-02Don't mask the pc because the Alpha predecoder needs it to set the PAL mode ↵Gabe Black
bit in the ExtMachInst. --HG-- extra : convert_revision : 87dc6e6b2281b6a11a0c0e8320b7f4acc29f6fb8
2007-06-01cast sizeof(MachInst) to Addr before generating a maskAli Saidi
--HG-- extra : convert_revision : 1ae34a069bbd997a8f888f69415fbeaaf4ade0b3
2007-05-31Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/cpu/simple/base.cc: Hand merge --HG-- extra : convert_revision : a2902ef9d917d22ffb9c7dfa2fd444694a65240d
2007-05-31Assign traceData to be NULL at BaseSimpleCPU constructor.Vincentius Robby
Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls. exec tracing isn't needed for m5.fast binaries Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead. src/arch/sparc/miscregfile.cc: Moved MISCREG_GL, MISCREG_CWP, and MISCREG_TLB_DATA out of switch statement and use if blocks instead. src/cpu/simple/base.cc: Assign traceData to be NULL at BaseSimpleCPU constructor. Initialize a temporary variable for thread->readPC() at setupFetchRequest() to reduce function calls. exec tracing isn't needed for m5.fast binaries --HG-- extra : convert_revision : 5dc92fff05c9bde994f1e0f1bb40e11c44eb72c6
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-25Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 276d00a73b1834d5262129c3f7e0f7fae18e23bc
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
--HG-- extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-20Add new EventWrapper constructor that takes a Tick valueSteve Reinhardt
and schedules the event immediately. --HG-- extra : convert_revision : a84e729a5ef3632cbe6cff858c453c782707d983
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-14 17:25:44 +0000