gem5 - gem5

Age	Commit message (Expand)	Author
2014-01-24	arch, cpu: Add support for flattening misc register indexes.	Ali Saidi
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-01-12	x86: Changes to decoder, corrects 9376	Nilay Vaish
2013-01-07	cpu: Fix broken thread context handover	Andreas Sandberg
2013-01-07	cpu: Unify SimpleCPU and O3 CPU serialization code	Andreas Sandberg
2013-01-07	cpu: Implement a flat register interface in thread contexts	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-02-24	MEM: Make port proxies use references rather than pointers	Andreas Hansson
2012-02-10	SE/FS: Record the system pointer all the time for the simple CPU.	Gabe Black
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	Thread: Use inherited baseCpu rather than cpu in SimpleThread	Andreas Hansson
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-30	Merge with main repository.	Gabe Black
2012-01-30	MEM: Clean-up of Functional/Virtual/TranslatingPort remnants	Andreas Hansson
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2011-11-18	SE/FS: Get rid of includes of config/full_system.hh.	Gabe Black
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-10-31	SE/FS: Make the functions available from the TC consistent between SE and FS.	Gabe Black
2011-10-16	SE/FS: Build/expose vport in SE mode.	Gabe Black
2011-10-16	CPU: Make physPort and getPhysPort available in SE mode.	Gabe Black
2011-09-09	Decode: Pull instruction decoding out of the StaticInst class into its own.	Gabe Black
2011-06-19	simple-thread: give a name() function for debugging w/the SimpleThread object	Korey Sewell
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2010-08-23	CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflag	Min Kyu Jeong
2010-08-23	ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.	Min Kyu Jeong
2010-06-02	ARM: Implement ARM CPU interrupts	Ali Saidi
2010-06-02	Simple CPU: Make the FloatRegs trace flag do something.	Gabe Black
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-07-29	Simple CPU: Make the simple CPU handle the IntRegs trace flag.	Gabe Black
2009-07-08	Get rid of the unused get(Data\|Inst)Asid and (inst\|data)Asid functions.	Gabe Black
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
2009-07-08	Registers: Eliminate the ISA defined RegFile class.	Gabe Black
2009-07-08	Registers: Move the PCs out of the ISAs and into the CPUs.	Gabe Black
2009-07-08	ARM, Simple CPU: Fix an index and add assert checks.	Gabe Black
2009-07-08	Registers: Eliminate the ISA defined integer register file.	Gabe Black
2009-07-08	Registers: Eliminate the ISA defined floating point register file.	Gabe Black
2009-07-08	Registers: Get rid of the float register width parameter.	Gabe Black
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-05-17	includes: sort includes again	Nathan Binkert
2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
2009-04-15	Get rid of the Unallocated thread context state.	Steve Reinhardt