Age | Commit message (Expand) | Author |
2019-12-10 | arch,cpu,sim: Push syscall number determination up to processes. | Gabe Black |
2019-12-03 | cpu,sim-se: move error checks in syscall methods | Brandon Potter |
2019-11-26 | arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs. | Gabe Black |
2019-11-06 | cpu: Use std::array for registers in SimpleThread. | Gabe Black |
2019-10-25 | cpu: Get rid of the nextInstEventCount method. | Gabe Black |
2019-10-25 | cpu: Get rid of the serviceInstCountEvents method. | Gabe Black |
2019-10-25 | cpu: Switch off of the CPU's comInstEventQueue. | Gabe Black |
2019-10-25 | cpu: Make the ThreadContext a PCEventScope. | Gabe Black |
2019-05-30 | arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy. | Gabe Black |
2019-05-30 | cpu, sim: Return PortProxy &s from all the proxy accessors. | Gabe Black |
2019-05-11 | cpu: Add a memory access predicate | Giacomo Gabrielli |
2019-04-30 | cpu: alpha: Delete all occurrances of the simPalCheck function. | Gabe Black |
2019-04-30 | cpu: Remove hwrei from the generic interfaces. | Gabe Black |
2019-04-30 | arch: cpu: Track kernel stats using the base ISA agnostic type. | Gabe Black |
2019-04-24 | cpu,mem: missing override specifier | Andrea Mondelli |
2019-04-22 | cpu: Eliminate the ProxyThreadContext class. | Gabe Black |
2019-02-19 | cpu: Add ISA* getter in Thread interface | Giacomo Gabrielli |
2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
2019-01-16 | cpu: dev: sim: gpu-compute: Banish some ISA specific register types. | Gabe Black |
2018-12-22 | cpu: Stop using unions to store FP registers. | Gabe Black |
2018-12-20 | arch, cpu: Remove float type accessors. | Gabe Black |
2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
2017-02-27 | syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess s... | Brandon Potter |
2015-07-20 | syscall_emul: [patch 13/22] add system call retry capability | Brandon Potter |
2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
2015-07-26 | cpu: implements vector registers | Nilay Vaish |
2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
2015-02-16 | arch: Make readMiscRegNoEffect const throughout | Andreas Hansson |
2015-01-25 | cpu: Remove all notion that we know when the cpu is misspeculating. | Ali Saidi |
2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
2014-04-29 | arm: use condition code registers for ARM ISA | Curtis Dunham |
2014-01-24 | arch, cpu: Add support for flattening misc register indexes. | Ali Saidi |
2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
2013-01-12 | x86: Changes to decoder, corrects 9376 | Nilay Vaish |
2013-01-07 | cpu: Fix broken thread context handover | Andreas Sandberg |
2013-01-07 | cpu: Unify SimpleCPU and O3 CPU serialization code | Andreas Sandberg |
2013-01-07 | cpu: Implement a flat register interface in thread contexts | Andreas Sandberg |
2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg |
2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
2012-05-25 | Decode: Make the Decoder class defined per ISA. | Gabe Black |
2012-03-19 | gcc: Clean-up of non-C++0x compliant code, first steps | Andreas Hansson |
2012-03-09 | CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable | Geoffrey Blake |
2012-02-24 | MEM: Make port proxies use references rather than pointers | Andreas Hansson |
2012-02-10 | SE/FS: Record the system pointer all the time for the simple CPU. | Gabe Black |