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path: root/src/cpu/simple_thread.hh
AgeCommit message (Expand)Author
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
2019-05-30cpu, sim: Return PortProxy &s from all the proxy accessors.Gabe Black
2019-05-11cpu: Add a memory access predicateGiacomo Gabrielli
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-24cpu,mem: missing override specifierAndrea Mondelli
2019-04-22cpu: Eliminate the ProxyThreadContext class.Gabe Black
2019-02-19cpu: Add ISA* getter in Thread interfaceGiacomo Gabrielli
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2018-12-22cpu: Stop using unions to store FP registers.Gabe Black
2018-12-20arch, cpu: Remove float type accessors.Gabe Black
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-02-27syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess s...Brandon Potter
2015-07-20syscall_emul: [patch 13/22] add system call retry capabilityBrandon Potter
2015-10-12misc: Remove redundant compiler-specific definesAndreas Hansson
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2015-01-25cpu: Remove all notion that we know when the cpu is misspeculating.Ali Saidi
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-07cpu: Fix broken thread context handoverAndreas Sandberg
2013-01-07cpu: Unify SimpleCPU and O3 CPU serialization codeAndreas Sandberg
2013-01-07cpu: Implement a flat register interface in thread contextsAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-10SE/FS: Record the system pointer all the time for the simple CPU.Gabe Black
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31Thread: Use inherited baseCpu rather than cpu in SimpleThreadAndreas Hansson
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-30Merge with main repository.Gabe Black
2012-01-30MEM: Clean-up of Functional/Virtual/TranslatingPort remnantsAndreas Hansson
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2011-11-18SE/FS: Get rid of includes of config/full_system.hh.Gabe Black