Age | Commit message (Expand) | Author |
2009-02-10 | style | Nathan Binkert |
2009-02-10 | CPU: Prepare CPU models for the new in-order CPU model. | Korey Sewell |
2008-10-12 | X86: Make the MicroPC type 16 bit. | Gabe Black |
2008-10-12 | CPU: Make the highest order bit in the micro pc determine if it's combination... | Gabe Black |
2008-10-09 | O3: Generaize the O3 IMPL class so it isn't split out by ISA. | Gabe Black |
2008-10-09 | O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA. | Gabe Black |
2008-09-10 | style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul... | Ali Saidi |
2008-02-05 | Add base ARM code to M5 | Stephen Hines |
2007-11-13 | Add in files from merge-bare-iron, get them compiling in FS and SE mode | Korey Sewell |
2007-08-30 | Fix miscellaneous small typos. | Miles Kaufmann |
2007-08-08 | Port, StaticInst: Revert unnecessary changes. | Vincentius Robby |
2007-08-08 | alpha: Make the TLB cache to actually work. | Vincentius Robby |
2007-08-04 | StaticInst: Fix decode cache initialization. Cache functionality was negated. | Vincentius Robby |
2007-07-31 | Add a flag to indicate an instruction triggers a syscall in SE mode. | Gabe Black |
2007-06-14 | Modified instruction decode method. | Vincentius Robby |
2007-06-12 | Make microOp vs microop and macroOp vs macroop capitilization consistent. | Gabe Black |
2007-03-15 | Make the predecoder an object with it's own switched header file. Start addin... | Gabe Black |
2007-03-13 | Replaced makeExtMI with predecode. | Gabe Black |
2007-01-27 | While I'm waiting for legion to run make m5 compile with a few more compilers | Ali Saidi |
2007-01-16 | Modify ISA and staticInst to support a IsFirstMicroOp flag | Ali Saidi |
2006-10-12 | StaticInst support for microcode | Gabe Black |
2006-08-15 | Merge zizzer.eecs.umich.edu:/bk/newmem | Gabe Black |
2006-08-15 | Cleaned up include files and got rid of many using directives in header files. | Gabe Black |
2006-08-15 | Fixed ALPHA_FS by moving the remnants of isa_fullsys_traits.hh into arch/alph... | Gabe Black |
2006-08-11 | Pushed most of constants.hh back into isa_traits.hh and regfile.hh and create... | Gabe Black |
2006-07-23 | This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,... | Korey Sewell |
2006-07-06 | Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a s... | Korey Sewell |
2006-07-06 | more steps toward O3 SMT | Korey Sewell |
2006-06-11 | Edit Fetch DPRINT in simple CPU | Korey Sewell |
2006-06-06 | Change ExecContext to ThreadContext. This is being renamed to differentiate ... | Kevin Lim |
2006-06-02 | Merge ktlim@zizzer:/bk/newmem | Kevin Lim |
2006-05-31 | Updated Authors from bk prs info | Ali Saidi |
2006-05-30 | Merge ktlim@zizzer:/bk/m5 | Kevin Lim |
2006-05-22 | New directory structure: | Steve Reinhardt |