summaryrefslogtreecommitdiff
path: root/src/cpu/static_inst.hh
AgeCommit message (Expand)Author
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2011-09-09StaticInst: Merge StaticInst and StaticInstBase.Gabe Black
2011-09-09Decode: Pull instruction decoding out of the StaticInst class into its own.Gabe Black
2011-04-15includes: sort all includesNathan Binkert
2011-04-04CPU: Remove references to memory copy operationsAli Saidi
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
2010-12-07O3: Support squashing all state after special instructionAli Saidi
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-11-08ARM: Make all ARM uops delayed commit.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-09-14CPU: Trim unnecessary includes from some common files.Gabe Black
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-08-23CPU: Make the constants for StaticInst flags visible outside the class.Gabe Black
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
2009-05-12inorder-tlb-cunit: merge the TLB as implicit to any memory accessKorey Sewell
2009-02-25CPU: Add a flag to identify a read barrier to the static inst class.Gabe Black
2009-02-10styleNathan Binkert
2009-02-10CPU: Prepare CPU models for the new in-order CPU model.Korey Sewell
2008-10-12X86: Make the MicroPC type 16 bit.Gabe Black
2008-10-12CPU: Make the highest order bit in the micro pc determine if it's combination...Gabe Black
2008-10-09O3: Generaize the O3 IMPL class so it isn't split out by ISA.Gabe Black
2008-10-09O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.Gabe Black
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...Ali Saidi
2008-02-05Add base ARM code to M5Stephen Hines
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
2007-08-30Fix miscellaneous small typos.Miles Kaufmann
2007-08-08Port, StaticInst: Revert unnecessary changes.Vincentius Robby
2007-08-08alpha: Make the TLB cache to actually work.Vincentius Robby
2007-08-04StaticInst: Fix decode cache initialization. Cache functionality was negated.Vincentius Robby
2007-07-31Add a flag to indicate an instruction triggers a syscall in SE mode.Gabe Black
2007-06-14Modified instruction decode method.Vincentius Robby
2007-06-12Make microOp vs microop and macroOp vs macroop capitilization consistent.Gabe Black
2007-03-15Make the predecoder an object with it's own switched header file. Start addin...Gabe Black
2007-03-13Replaced makeExtMI with predecode.Gabe Black
2007-01-27While I'm waiting for legion to run make m5 compile with a few more compilersAli Saidi
2007-01-16Modify ISA and staticInst to support a IsFirstMicroOp flagAli Saidi
2006-10-12StaticInst support for microcodeGabe Black
2006-08-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
2006-08-15Fixed ALPHA_FS by moving the remnants of isa_fullsys_traits.hh into arch/alph...Gabe Black
2006-08-11Pushed most of constants.hh back into isa_traits.hh and regfile.hh and create...Gabe Black
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...Korey Sewell
2006-07-06Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a s...Korey Sewell
2006-07-06more steps toward O3 SMTKorey Sewell
2006-06-11Edit Fetch DPRINT in simple CPUKorey Sewell
2006-06-06Change ExecContext to ThreadContext. This is being renamed to differentiate ...Kevin Lim
2006-06-02Merge ktlim@zizzer:/bk/newmemKevin Lim
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 03:03:58 +0000