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path: root/src/cpu/static_inst.hh
AgeCommit message (Expand)Author
2018-06-14cpu: add a new instruction type 'Atomic'Tuan Ta
2018-03-26arch: Add a virtual asBytes function to the StaticInst class.Gabe Black
2017-12-22cpu: Add a pointer to a generic Nop StaticInst.Gabe Black
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-07-05arch: ISA parser additions of vector registersRekai Gonzalez-Alberquilla
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-03-02cpu: o3 register renaming request handling improvedRekai
2015-01-25arm: always set the IsFirstMicroop flagAli Saidi
2014-11-14arm: Fixes based on UBSan and static analysisAndreas Hansson
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-07-23cpu: `Minor' in-order CPU modelAndrew Bardsley
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-09-04arch: Header clean up for NOISA resurrectionAndreas Hansson
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2011-09-09StaticInst: Merge StaticInst and StaticInstBase.Gabe Black
2011-09-09Decode: Pull instruction decoding out of the StaticInst class into its own.Gabe Black
2011-04-15includes: sort all includesNathan Binkert
2011-04-04CPU: Remove references to memory copy operationsAli Saidi
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
2010-12-07O3: Support squashing all state after special instructionAli Saidi
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-11-08ARM: Make all ARM uops delayed commit.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-09-14CPU: Trim unnecessary includes from some common files.Gabe Black
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-08-23CPU: Make the constants for StaticInst flags visible outside the class.Gabe Black
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
2009-05-12inorder-tlb-cunit: merge the TLB as implicit to any memory accessKorey Sewell
2009-02-25CPU: Add a flag to identify a read barrier to the static inst class.Gabe Black
2009-02-10styleNathan Binkert
2009-02-10CPU: Prepare CPU models for the new in-order CPU model.Korey Sewell
2008-10-12X86: Make the MicroPC type 16 bit.Gabe Black
2008-10-12CPU: Make the highest order bit in the micro pc determine if it's combination...Gabe Black
2008-10-09O3: Generaize the O3 IMPL class so it isn't split out by ISA.Gabe Black
2008-10-09O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.Gabe Black
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...Ali Saidi
2008-02-05Add base ARM code to M5Stephen Hines
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell