| Age | Commit message (Expand) | Author |
|---|
| 2018-06-14 | cpu: add a new instruction type 'Atomic' | Tuan Ta |
| 2018-03-26 | arch: Add a virtual asBytes function to the StaticInst class. | Gabe Black |
| 2017-12-22 | cpu: Add a pointer to a generic Nop StaticInst. | Gabe Black |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-07-05 | arch: ISA parser additions of vector registers | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-03-02 | cpu: o3 register renaming request handling improved | Rekai |
| 2015-01-25 | arm: always set the IsFirstMicroop flag | Ali Saidi |
| 2014-11-14 | arm: Fixes based on UBSan and static analysis | Andreas Hansson |
| 2014-10-16 | arch: Use shared_ptr for all Faults | Andreas Hansson |
| 2014-09-03 | arch, cpu: Factor out the ExecContext into a proper base class | Andreas Sandberg |
| 2014-07-23 | cpu: `Minor' in-order CPU model | Andrew Bardsley |
| 2014-05-09 | cpu: Add flag name printing to StaticInst | Andrew Bardsley |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2013-09-04 | arch: Header clean up for NOISA resurrection | Andreas Hansson |
| 2012-11-02 | sim: Include object header files in SWIG interfaces | Andreas Sandberg |
| 2012-03-19 | gcc: Clean-up of non-C++0x compliant code, first steps | Andreas Hansson |
| 2012-01-31 | clang: Enable compiling gem5 using clang 2.9 and 3.0 | Koan-Sin Tan |
| 2011-09-09 | StaticInst: Merge StaticInst and StaticInstBase. | Gabe Black |
| 2011-09-09 | Decode: Pull instruction decoding out of the StaticInst class into its own. | Gabe Black |
| 2011-04-15 | includes: sort all includes | Nathan Binkert |
| 2011-04-04 | CPU: Remove references to memory copy operations | Ali Saidi |
| 2011-03-17 | ARM: Fix subtle bug in LDM. | Ali Saidi |
| 2011-02-03 | Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh. | Gabe Black |
| 2010-12-07 | O3: Support squashing all state after special instruction | Ali Saidi |
| 2010-11-08 | ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. | Ali Saidi |
| 2010-11-08 | ARM: Make all ARM uops delayed commit. | Ali Saidi |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black |
| 2010-09-14 | CPU: Trim unnecessary includes from some common files. | Gabe Black |
| 2010-09-13 | Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. | Gabe Black |
| 2010-08-23 | CPU: Make the constants for StaticInst flags visible outside the class. | Gabe Black |
| 2009-09-23 | arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh | Nathan Binkert |
| 2009-05-17 | includes: sort includes again | Nathan Binkert |
| 2009-05-17 | types: Move stuff for global types into src/base/types.hh | Nathan Binkert |
| 2009-05-12 | inorder-tlb-cunit: merge the TLB as implicit to any memory access | Korey Sewell |
| 2009-02-25 | CPU: Add a flag to identify a read barrier to the static inst class. | Gabe Black |
| 2009-02-10 | style | Nathan Binkert |
| 2009-02-10 | CPU: Prepare CPU models for the new in-order CPU model. | Korey Sewell |
| 2008-10-12 | X86: Make the MicroPC type 16 bit. | Gabe Black |
| 2008-10-12 | CPU: Make the highest order bit in the micro pc determine if it's combination... | Gabe Black |
| 2008-10-09 | O3: Generaize the O3 IMPL class so it isn't split out by ISA. | Gabe Black |
| 2008-10-09 | O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA. | Gabe Black |
| 2008-09-10 | style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul... | Ali Saidi |
| 2008-02-05 | Add base ARM code to M5 | Stephen Hines |
| 2007-11-13 | Add in files from merge-bare-iron, get them compiling in FS and SE mode | Korey Sewell |
