gem5 - gem5

Age	Commit message (Expand)	Author
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-10-15	memtest: move check on outstanding requests	Nilay Vaish
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-02-24	MEM: Move all read/write blob functions from Port to PortProxy	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-12-21	memtest: delete some crufty dead code	Steve Reinhardt
2010-08-25	memtest: fix/cleanup functional access testing	Steve Reinhardt
2010-08-24	testers: move testers to a new directory	Brad Beckmann