gem5 - gem5

Age	Commit message (Expand)	Author
2018-04-27	sim,cpu,mem,arch: Introduced MasterInfo data structure	Giacomo Travaglini
2017-06-20	cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper	Sean Wilson
2016-11-09	style: [patch 3/22] reduce include dependencies in some headers	Brandon Potter
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2016-06-06	stats: Fixing regStats function for some SimObjects	David Guillen Fandos
2016-04-07	mem: Remove threadId from memory request class	Mitch Hayenga
2016-04-07	Revert to 74c1e6513bd0 (sim: Thermal support for Linux)	Andreas Sandberg
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
2016-04-05	mem: Remove threadId from memory request class	Mitch Hayenga
2014-11-18	power: Add power states to ClockedObject	Akash Bagdia
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2015-02-11	cpu: Tidy up the MemTest and make false sharing more obvious	Andreas Hansson
2015-01-22	mem: Clean up Request initialisation	Andreas Hansson
2014-12-02	mem: Assume all dynamic packet data is array allocated	Andreas Hansson
2014-12-02	mem: Add const getters for write packet data	Andreas Hansson
2014-09-19	misc: Use safe_cast when assumptions are made about return value	Andreas Hansson
2014-09-03	base: Use the global Mersenne twister throughout	Andreas Hansson
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-10-15	memtest: move check on outstanding requests	Nilay Vaish
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-02-24	MEM: Move all read/write blob functions from Port to PortProxy	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-12-21	memtest: delete some crufty dead code	Steve Reinhardt
2010-08-25	memtest: fix/cleanup functional access testing	Steve Reinhardt
2010-08-24	testers: move testers to a new directory	Brad Beckmann