gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-03	base: Use the global Mersenne twister throughout	Andreas Hansson
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-04-05	NetworkTest: remove unnecessary memory allocation	Tushar Krishna
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	Scons: Remove Werror=False in SConscript files	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert
2011-05-07	NetworkTest: added sim_cycles parameter to the network tester.	Tushar Krishna
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-22	This patch fixes a build error in networktest.cc that occurs with gcc4.2	Tushar Krishna
2011-03-21	This patch adds the network tester for simple and garnet networks.	Tushar Krishna