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path: root/src/cpu/testers/traffic_gen/traffic_gen.cc
AgeCommit message (Expand)Author
2014-09-20cpu: Update DRAM traffic genWendy Elsasser
2014-09-09misc: Fix a number of unitialised variables and membersAndreas Hansson
2014-09-03base: Use the global Mersenne twister throughoutAndreas Hansson
2014-08-10cpu: Ensure the traffic generator suppresses non-memory packetsAndreas Hansson
2014-03-23cpu: DRAM Traffic GeneratorNeha Agarwal
2014-03-23cpu: Add basic check to TrafficGen initial stateStan Czerniawski
2014-01-29cpu: fix bug when TrafficGen deschedules eventXiangyu Dong
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-05-30cpu: Check that minimum TrafficGen period is less than max periodSascha Bischoff
2013-05-30cpu: Fix bug when reading in TrafficGen state transitionsSascha Bischoff
2013-05-30cpu: Add request elasticity to the traffic generatorAndreas Hansson
2013-05-30cpu: Block traffic generator when requests have to retryAndreas Hansson
2013-05-30cpu: Move traffic generator sending out of generator statesAndreas Hansson
2013-05-30cpu: Fold together the StateGraph and the TrafficGenAndreas Hansson
2013-04-22cpu: Make the generators usable outside the TrafficGen moduleAndreas Hansson
2013-03-12cpu: Fix state transition bug in the traffic generatorAndreas Sandberg
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-01-07cpu: Share the send functionality between traffic generatorsAndreas Hansson
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
2013-01-07cpu: Encapsulate traffic generator input in a streamAndreas Hansson
2013-01-07cpu: Fix the traffic gen read percentageAndreas Hansson
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generatorAndreas Hansson