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path: root/src/cpu/testers
AgeCommit message (Expand)Author
2014-09-01ruby: eliminate type TimeNilay Vaish
2014-08-10cpu: Ensure the traffic generator suppresses non-memory packetsAndreas Hansson
2014-03-23cpu: DRAM Traffic GeneratorNeha Agarwal
2014-03-23cpu: Add basic check to TrafficGen initial stateStan Czerniawski
2014-01-29cpu: fix bug when TrafficGen deschedules eventXiangyu Dong
2013-08-19cpu: Fix TrafficGen trace playbackSascha Bischoff
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-05-30cpu: Check that minimum TrafficGen period is less than max periodSascha Bischoff
2013-05-30cpu: Fix bug when reading in TrafficGen state transitionsSascha Bischoff
2013-05-30cpu: Add request elasticity to the traffic generatorAndreas Hansson
2013-05-30cpu: Block traffic generator when requests have to retryAndreas Hansson
2013-05-30cpu: Move traffic generator sending out of generator statesAndreas Hansson
2013-05-30cpu: Fold together the StateGraph and the TrafficGenAndreas Hansson
2013-04-23cpu: Fix TraceGen flag initalisationAndreas Hansson
2013-04-22cpu: Use request flags in trace playbackAndreas Hansson
2013-04-22cpu: Make the generators usable outside the TrafficGen moduleAndreas Hansson
2013-03-12cpu: Fix state transition bug in the traffic generatorAndreas Sandberg
2013-02-19scons: Fix warnings issued by clang 3.2svn (XCode 4.6)Andreas Hansson
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-01-17ruby: remove calls to g_system_ptr->getTime()Nilay Vaish
2013-01-07cpu: Share the send functionality between traffic generatorsAndreas Hansson
2013-01-07cpu: Add support for protobuf input for the trace generatorAndreas Hansson
2013-01-07cpu: Encapsulate traffic generator input in a streamAndreas Hansson
2013-01-07cpu: Fix the traffic gen read percentageAndreas Hansson
2012-12-11ruby: modify the directed tester to read/write streamsNilay Vaish
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-10-15memtest: move check on outstanding requestsNilay Vaish
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generatorAndreas Hansson
2012-09-11Ruby: Use uint8_t instead of uint8 everywhereNilay Vaish
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-27Ruby: Remove RubyEventQueueNilay Vaish
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-07-10ruby: remove the cpu assumptions for the random testerBrad Beckmann
2012-06-05sim: Remove FastAllocAli Saidi
2012-05-30Packet: Unify the use of PortID in packet and portAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-25MEM: Add the PortId type and a corresponding id field to PortAndreas Hansson
2012-04-14Ruby: Use MasterPort base-class pointers where possibleAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-06rubytest: remove spurious printfBrad Beckmann
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
2012-04-05NetworkTest: remove unnecessary memory allocationTushar Krishna
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22Scons: Remove Werror=False in SConscript filesAndreas Hansson
2012-02-24Ruby: Simplify tester ports by not using SimpleTimingPortAndreas Hansson
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