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path: root/src/cpu/testers
AgeCommit message (Expand)Author
2018-12-04base, sim: Add missing destructorsNikos Nikoleris
2018-08-24cpu: Stream/SubstreamID support in TrafficGenGiacomo Travaglini
2018-08-24cpu: Turn BaseTrafficGen numSuppressed into a statMichiel W. van Tol
2018-08-21misc: Appease GCC 8Jason Lowe-Power
2018-08-17scons,ruby: do not generate unnecessary filesBrandon Potter
2018-07-25cpu: Warn when (un)serializing a traffic generatorGiacomo Travaglini
2018-07-25cpu: Allow creation of traffic gen from generic SimObjectsGiacomo Travaglini
2018-07-13cpu: Add a Python-enabled traffic generatorAndreas Sandberg
2018-07-13cpu: Support trace termination in BaseTrafficGenAndreas Sandberg
2018-07-13cpu: Unify error handling for address generatorsAndreas Sandberg
2018-07-13cpu: Split the traffic generator into two classesAndreas Sandberg
2018-06-28cpu: Remove reduntant protobuf includesAndreas Sandberg
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
2018-03-23ruby: Make sure addresses print in hexJason Lowe-Power
2017-12-20cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh.Gabe Black
2017-12-19cpu-tester: Added ExitGen to TrafficGenRiken Gohil
2017-12-19cpu-tester: Refactoring traffic generators into separate files.Riken Gohil
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-07-12testers: Refactor some Event subclasses to lambdasSean Wilson
2017-06-20cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2016-11-09style: [patch 3/22] reduce include dependencies in some headersBrandon Potter
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-12-05cpu: Change traffic generators to use different values for writesNikos Nikoleris
2016-10-06ruby: rename networktest to garnet_synthetic_traffic.Tushar Krishna
2016-06-20mem: Resolve TrafficGen trace relative to the configAndreas Sandberg
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-05-26cpu: Add a basic progress check to the TrafficGenAndreas Hansson
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-07Revert to 74c1e6513bd0 (sim: Thermal support for Linux)Andreas Sandberg
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2014-11-18power: Add power states to ClockedObjectAkash Bagdia
2016-03-20cpu: warn if TrafficGen is suppressing a large numer of packetsAndreas Hansson
2016-02-24cpu: TraceGen fix for tick frequency checkMatteo Andreozzi
2016-02-06style: remove trailing whitespaceSteve Reinhardt
2015-07-20ruby: more flexible ruby tester supportBrad Beckmann
2015-11-22cpu: Fix memory leak in traffic generatorAndreas Hansson
2015-10-12misc: Add explicit overrides and fix other clang >= 3.5 issuesAndreas Hansson
2015-10-12misc: Remove redundant compiler-specific definesAndreas Hansson
2015-08-29ruby: eliminate type uint64 and int64Nilay Vaish
2015-08-19ruby: reverts to changeset: bf82f1f7b040Nilay Vaish
2015-08-14ruby: eliminate type uint64 and int64Nilay Vaish
2015-08-14ruby: replace Address by AddrNilay Vaish
2015-08-11ruby: drop some redundant includesNilay Vaish
2015-07-10ruby: replace global g_abs_controls with per-RubySystem varBrandon Potter
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
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