| Age | Commit message (Expand) | Author |
|---|
| 2019-04-28 | mem: Minimize the use of MemObject. | Gabe Black |
| 2019-03-23 | misc: missing override specifier | Andrea Mondelli |
| 2019-03-19 | arch, cpu, dev, gpu, mem, sim, python: start using getPort. | Gabe Black |
| 2019-02-12 | python: Don't assume SimObjects live in the global namespace | Andreas Sandberg |
| 2018-12-04 | base, sim: Add missing destructors | Nikos Nikoleris |
| 2018-08-24 | cpu: Stream/SubstreamID support in TrafficGen | Giacomo Travaglini |
| 2018-08-24 | cpu: Turn BaseTrafficGen numSuppressed into a stat | Michiel W. van Tol |
| 2018-08-21 | misc: Appease GCC 8 | Jason Lowe-Power |
| 2018-08-17 | scons,ruby: do not generate unnecessary files | Brandon Potter |
| 2018-07-25 | cpu: Warn when (un)serializing a traffic generator | Giacomo Travaglini |
| 2018-07-25 | cpu: Allow creation of traffic gen from generic SimObjects | Giacomo Travaglini |
| 2018-07-13 | cpu: Add a Python-enabled traffic generator | Andreas Sandberg |
| 2018-07-13 | cpu: Support trace termination in BaseTrafficGen | Andreas Sandberg |
| 2018-07-13 | cpu: Unify error handling for address generators | Andreas Sandberg |
| 2018-07-13 | cpu: Split the traffic generator into two classes | Andreas Sandberg |
| 2018-06-28 | cpu: Remove reduntant protobuf includes | Andreas Sandberg |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-06-11 | misc: Substitute pointer to Request with aliased RequestPtr | Giacomo Travaglini |
| 2018-04-27 | sim,cpu,mem,arch: Introduced MasterInfo data structure | Giacomo Travaglini |
| 2018-03-23 | ruby: Make sure addresses print in hex | Jason Lowe-Power |
| 2017-12-20 | cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh. | Gabe Black |
| 2017-12-19 | cpu-tester: Added ExitGen to TrafficGen | Riken Gohil |
| 2017-12-19 | cpu-tester: Refactoring traffic generators into separate files. | Riken Gohil |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-07-12 | testers: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-06-20 | cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
| 2016-11-09 | style: [patch 3/22] reduce include dependencies in some headers | Brandon Potter |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2016-12-05 | cpu: Change traffic generators to use different values for writes | Nikos Nikoleris |
| 2016-10-06 | ruby: rename networktest to garnet_synthetic_traffic. | Tushar Krishna |
| 2016-06-20 | mem: Resolve TrafficGen trace relative to the config | Andreas Sandberg |
| 2016-06-06 | stats: Fixing regStats function for some SimObjects | David Guillen Fandos |
| 2016-06-06 | sim: Call regStats of base-class as well | Stephan Diestelhorst |
| 2016-05-26 | cpu: Add a basic progress check to the TrafficGen | Andreas Hansson |
| 2016-04-07 | mem: Remove threadId from memory request class | Mitch Hayenga |
| 2016-04-07 | Revert to 74c1e6513bd0 (sim: Thermal support for Linux) | Andreas Sandberg |
| 2016-04-06 | Revert power patch sets with unexpected interactions | Andreas Sandberg |
| 2016-04-05 | mem: Remove threadId from memory request class | Mitch Hayenga |
| 2014-11-18 | power: Add power states to ClockedObject | Akash Bagdia |
| 2016-03-20 | cpu: warn if TrafficGen is suppressing a large numer of packets | Andreas Hansson |
| 2016-02-24 | cpu: TraceGen fix for tick frequency check | Matteo Andreozzi |
| 2016-02-06 | style: remove trailing whitespace | Steve Reinhardt |
| 2015-07-20 | ruby: more flexible ruby tester support | Brad Beckmann |
| 2015-11-22 | cpu: Fix memory leak in traffic generator | Andreas Hansson |
| 2015-10-12 | misc: Add explicit overrides and fix other clang >= 3.5 issues | Andreas Hansson |
| 2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
| 2015-08-29 | ruby: eliminate type uint64 and int64 | Nilay Vaish |
| 2015-08-19 | ruby: reverts to changeset: bf82f1f7b040 | Nilay Vaish |
| 2015-08-14 | ruby: eliminate type uint64 and int64 | Nilay Vaish |
| 2015-08-14 | ruby: replace Address by Addr | Nilay Vaish |
