gem5 - gem5

Age	Commit message (Expand)	Author
2017-07-05	cpu: Added interface for vector reg file	Rekai Gonzalez-Alberquilla
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2016-09-13	sim: Refactor quiesce and remove FS asserts	Michael LeBeane
2015-08-07	base: Declare a type for context IDs	Andreas Sandberg
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-01-07	cpu: Fix broken thread context handover	Andreas Sandberg
2013-01-07	cpu: Unify SimpleCPU and O3 CPU serialization code	Andreas Sandberg
2011-10-31	SE/FS: Make the functions available from the TC consistent between SE and FS.	Gabe Black
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-11-02	make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered	Lisa Hsu
2007-11-08	CPU: Add function to explictly compare thread contexts after copying.	Ali Saidi