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path: root/src/cpu/thread_context.hh
AgeCommit message (Expand)Author
2016-09-13sim: Refactor quiesce and remove FS assertsMichael LeBeane
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2015-01-25cpu: Remove all notion that we know when the cpu is misspeculating.Ali Saidi
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-03-07cpu: Make CPU and ThreadContext getters constAndreas Hansson
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-01-07cpu: Fix broken thread context handoverAndreas Sandberg
2013-01-07cpu: Unify SimpleCPU and O3 CPU serialization codeAndreas Sandberg
2013-01-07cpu: Implement a flat register interface in thread contextsAndreas Sandberg
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2011-10-31SE/FS: Make the functions available from the TC consistent between SE and FS.Gabe Black
2011-10-30SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs.Gabe Black
2011-10-16SE/FS: Include getMemPort in FS.Gabe Black
2011-10-16SE/FS: Build/expose vport in SE mode.Gabe Black
2011-10-16CPU: Make physPort and getPhysPort available in SE mode.Gabe Black
2011-09-09Decode: Pull instruction decoding out of the StaticInst class into its own.Gabe Black
2011-04-15includes: sort all includesNathan Binkert
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-09-14CPU: Trim unnecessary includes from some common files.Gabe Black
2010-09-13CPU: Get rid of the now unnecessary getInst/setInst family of functions.Gabe Black
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
2009-07-08Registers: Eliminate the ISA defined RegFile class.Gabe Black
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
2009-04-15Get rid of the Unallocated thread context state.Steve Reinhardt
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-02-27Processes: Make getting and setting system call arguments part of a process o...Gabe Black
2009-01-19thread_context: move getSystemPtr so SE mode can get to it.Nathan Binkert
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu