gem5 - gem5

Age	Commit message (Expand)	Author
2018-04-27	sim,cpu,mem,arch: Introduced MasterInfo data structure	Giacomo Travaglini
2017-06-20	cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper	Sean Wilson
2017-03-16	cpu: Print progress messages in Trace CPU	Radhika Jagtap
2016-09-15	cpu: Support exit when any one Trace CPU completes replay	Radhika Jagtap
2016-09-15	cpu: Adjust for trace offset and fix stats	Radhika Jagtap
2016-09-15	cpu: Add frequency scaling to the Trace CPU	Radhika Jagtap
2016-04-07	mem: Remove threadId from memory request class	Mitch Hayenga
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
2016-04-05	mem: Remove threadId from memory request class	Mitch Hayenga
2016-01-11	scons: Enable -Wextra by default	Andreas Hansson
2015-12-07	cpu: Support virtual addr in elastic traces	Radhika Jagtap
2015-12-07	cpu: Create record type enum for elastic traces	Radhika Jagtap
2015-12-07	cpu: Add TraceCPU to playback elastic traces	Radhika Jagtap
2013-05-30	cpu: Prune the stale TraceCPU	Andreas Hansson
2011-04-15	includes: sort all includes	Nathan Binkert
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2009-04-20	request: rename INST_READ to INST_FETCH.	Steve Reinhardt
2008-02-06	Make the Event::description() a const function	Stephen Hines
2007-09-28	Rename cycles() function to ticks()	Ali Saidi
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-06-30	Event descriptions should not end in "event"	Steve Reinhardt
2007-03-10	Rework the way SCons recurses into subdirectories, making it	Nathan Binkert
2006-06-09	Move main control from C++ into Python.	Steve Reinhardt
2006-05-31	Updated Authors from bk prs info	Ali Saidi
2006-05-22	New directory structure:	Steve Reinhardt