| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-05-05 | mem, cpu: Add a separate flag for strictly ordered memory | Andreas Sandberg |
| 2015-02-11 | sim: Move the BaseTLB to src/arch/generic/ | Andreas Sandberg |
| 2014-09-19 | arch: Pass faults by const reference where possible | Andreas Hansson |
| 2014-04-23 | cpu: Fix setTranslateLatency() bug for squashed instructions | Mitchell Hayenga |
| 2014-01-24 | mem: track per-request latencies and access depths in the cache hierarchy | Matt Horsnell |
| 2012-09-25 | ARM: Squash outstanding walks when instructions are squashed. | Ali Saidi |
| 2011-08-07 | Translation: Use a pointer type as the template argument. | Gabe Black |
| 2011-02-11 | O3: Enhance data address translation by supporting hardware page table walkers. | Giacomo Gabrielli |
| 2010-09-13 | Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. | Gabe Black |
| 2010-03-25 | CPU: Added comments to address translation classes. | Timothy M. Jones |
| 2010-02-12 | BaseDynInst: Make the TLB translation timing instead of atomic. | Timothy M. Jones |
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index : gem5 | |
| gem5 |
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