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path: root/src/cpu
AgeCommit message (Expand)Author
2019-05-11try not expose if L1 hitis-ift-cachehitIru Cai
2019-04-22fix the violation checking for IFT+fenceIru Cai
2019-04-17add a trackBranch optionIru Cai
2019-04-17IFT for fence schemeIru Cai
2019-04-16track instruction after tainted branchesIru Cai
2019-04-15Add IFT debug flagsIru Cai
2019-04-12add IEW DPRINTFIru Cai
2019-04-12keep time to expose as original scheme when inst->needPostFetch()Iru Cai
2019-04-12add IFT optionsIru Cai
2019-04-10clear taint when previous branch resolvedIru Cai
2019-04-08we need to ++loadsToVLD when (!inst->readyToExpose() && inst->needPostFetch())Iru Cai
2019-04-08implement taint propagationIru Cai
2019-04-03check loads using tainted registers, set USL dst as taintedIru Cai
2019-04-02methods to set taintIru Cai
2019-04-02add taint mapIru Cai
2019-04-02print load instIru Cai
2019-04-01fix getvaddr nullptr stuff, add a non-spec load printingis-rebase11-LSQUnitIru Cai
2019-03-21Request::getVaddr()Iru Cai
2019-03-20invisispec-1.0 sourceIru Cai
2018-12-11cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctorTony Gutierrez
2018-12-04base, sim: Add missing destructorsNikos Nikoleris
2018-12-03cpu: Change raw pointers to STL ContainersRekai Gonzalez-Alberquilla
2018-11-28cpu: Added new stats to TAGE and LTAGE branch predictorsPau Cabre
2018-11-28cpu: split LTAGE implementation into a base TAGE and a derived LTAGEPau Cabre
2018-11-28cpu,arch-arm: Initialise data membersRekai Gonzalez-Alberquilla
2018-11-27arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.Gabe Black
2018-11-22cpu: Made LTAGE parameters configurablePau Cabre
2018-11-22cpu: Fixed useful counter handling in LTAGEPau Cabre
2018-11-22cpu: Fixes on the loop predictor part of LTAGEPau Cabre
2018-11-17cpu: Fix LTAGE max number of allocations on updatePau Cabre
2018-11-17configs: Added an option for choosing branch predictor typePau Cabre
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
2018-11-14cpu: Fixed ratio of pred to hyst bits for LTAGE BimodalPau Cabre
2018-11-13cpu: Fixed PC shifting on LTAGE branch predictorPau Cabre
2018-10-09cpu: Fix MinorCPU executing Crypto InstructionsGiacomo Travaglini
2018-10-09arch-arm: AArch32 Crypto AESMatt Horsnell
2018-10-09arch-arm: AArch32 Crypto SHAMatt Horsnell
2018-10-01cpu: Fix typo in header guard for Noncaching cpuGiacomo Travaglini
2018-09-13Fix SConstruct for asan buildEarl Ou
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
2018-08-24cpu: Stream/SubstreamID support in TrafficGenGiacomo Travaglini
2018-08-24cpu: Turn BaseTrafficGen numSuppressed into a statMichiel W. van Tol
2018-08-21misc: Appease GCC 8Jason Lowe-Power
2018-08-17scons,ruby: do not generate unnecessary filesBrandon Potter
2018-08-10cpu: Add hash functionality for RegId classBradley Wang
2018-08-10cpu: Removed unnecessary file reg_class_impl.hhBradley Wang
2018-07-25cpu: Warn when (un)serializing a traffic generatorGiacomo Travaglini
2018-07-25cpu: Allow creation of traffic gen from generic SimObjectsGiacomo Travaglini
2018-07-24cpu-o3: Missing freeing the heads of DepGraph in IQ squashingHanhwi Jang
2018-07-13cpu: Add a Python-enabled traffic generatorAndreas Sandberg