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cpu
Age
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Author
2016-01-17
cpu. arch: add initiateMemRead() to ExecContext interface
Steve Reinhardt
2016-01-17
cpu: remove unnecessary data ptr from O3 internal read() funcs
Steve Reinhardt
2016-01-11
scons: Enable -Wextra by default
Andreas Hansson
2015-12-31
mem: Make cache terminology easier to understand
Andreas Hansson
2015-07-20
ruby: more flexible ruby tester support
Brad Beckmann
2015-12-07
cpu: Support virtual addr in elastic traces
Radhika Jagtap
2015-12-07
cpu: Create record type enum for elastic traces
Radhika Jagtap
2015-12-07
cpu: Add TraceCPU to playback elastic traces
Radhika Jagtap
2015-12-07
proto, probe: Add elastic trace probe to o3 cpu
Radhika Jagtap
2015-12-07
probe: Add probe in Fetch, IEW, Rename and Commit
Radhika Jagtap
2015-12-04
cpu: fix unitialized variable which may cause assertion failure
Pau Cabre
2015-11-22
cpu: Fix base FP and CC register index in o3 insertThread()
Nathanael Premillieu
2015-11-22
cpu: Fix memory leak in traffic generator
Andreas Hansson
2015-11-20
cpu: Enforce 1 interrupt controller per thread
Andreas Sandberg
2015-11-16
o3: drop unused statistic wbPenalized and wbPenalizedRate
Nilay Vaish
2015-10-12
misc: Add explicit overrides and fix other clang >= 3.5 issues
Andreas Hansson
2015-10-12
misc: Remove redundant compiler-specific defines
Andreas Hansson
2015-10-09
isa: Add parameter to pick different decoder inside ISA
Rekai Gonzalez Alberquilla
2015-10-06
sim: add ExecMacro to Exec* compound debug flags
Steve Reinhardt
2015-09-30
base: remove Trace::enabled flag
Curtis Dunham
2015-09-30
cpu,isa,mem: Add per-thread wakeup logic
Mitch Hayenga
2015-09-30
isa,cpu: Add support for FS SMT Interrupts
Mitch Hayenga
2015-09-30
cpu: Add per-thread monitors
Mitch Hayenga
2015-09-30
config,cpu: Add SMT support to Atomic and Timing CPUs
Mitch Hayenga
2015-09-30
cpu: Change thread assignments for heterogenous SMT
Mitch Hayenga
2015-09-15
cpu: pred: Local Predictor Reset in Tournament Predictor
Andrew Lukefahr
2015-09-15
cpu, o3: consider split requests for LSQ checksnoop operations
Hongil Yoon
2015-08-29
ruby: eliminate type uint64 and int64
Nilay Vaish
2015-08-21
mem: Reflect that packet address and size are always valid
Andreas Hansson
2015-08-21
cpu: Move invldPid constant from Request to BaseCPU
Andreas Hansson
2015-08-19
ruby: reverts to changeset: bf82f1f7b040
Nilay Vaish
2015-08-14
ruby: eliminate type uint64 and int64
Nilay Vaish
2015-08-14
ruby: replace Address by Addr
Nilay Vaish
2015-08-11
ruby: drop some redundant includes
Nilay Vaish
2015-08-07
base: Declare a type for context IDs
Andreas Sandberg
2015-07-20
cpu: Fixed a bug on where to fetch the next instruction from
David Hashe
2015-07-31
cpu: Update debug message from Fetch1 isDrained() in Minor
Andreas Sandberg
2015-07-31
cpu: Fix Minor drain issues when switched out
Andreas Sandberg
2015-07-30
cpu: Only activate thread 0 in Minor if the CPU is active
Andreas Sandberg
2015-07-30
cpu: Fix drain issues in the Minor CPU
Andreas Sandberg
2015-07-30
cpu: Fix issue identified by UBSan
Andreas Hansson
2015-07-28
revert 5af8f40d8f2c
Nilay Vaish
2015-07-26
cpu: implements vector registers
Nilay Vaish
2015-07-26
cpu: o3: slight correction to identation in rename_impl.hh
Nilay Vaish
2015-07-10
ruby: replace global g_abs_controls with per-RubySystem var
Brandon Potter
2015-07-07
sim: Refactor and simplify the drain API
Andreas Sandberg
2015-07-07
sim: Make the drain state a global typed enum
Andreas Sandberg
2015-07-07
sim: Refactor the serialization base class
Andreas Sandberg
2015-07-04
o3: correct the number of cc registers in rename map
Nilay Vaish
2015-06-01
kvm, arm: Add support for aarch64
Andreas Sandberg
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