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2019-04-22fix the violation checking for IFT+fenceIru Cai
When using IFT, fenceDelay means the load is deferred, but some load can be between fences and executed, so fenceDelayed instructions should be checked.
2019-04-17add a trackBranch optionIru Cai
2019-04-17IFT for fence schemeIru Cai
2019-04-16track instruction after tainted branchesIru Cai
2019-04-15Add IFT debug flagsIru Cai
2019-04-12add IEW DPRINTFIru Cai
2019-04-12keep time to expose as original scheme when inst->needPostFetch()Iru Cai
because when inst->needPostFetch(), it means that the spec load is already issued this also fixes the mysterious bug caused by the IFT code
2019-04-12add IFT optionsIru Cai
2019-04-10clear taint when previous branch resolvedIru Cai
2019-04-08we need to ++loadsToVLD when (!inst->readyToExpose() && inst->needPostFetch())Iru Cai
2019-04-08implement taint propagationIru Cai
2019-04-03check loads using tainted registers, set USL dst as taintedIru Cai
2019-04-02methods to set taintIru Cai
2019-04-02add taint mapIru Cai
2019-04-02print load instIru Cai
2019-04-01fix getvaddr nullptr stuff, add a non-spec load printingis-rebase11-LSQUnitIru Cai
2019-03-21Request::getVaddr()Iru Cai
Change-Id: Ife5c04941a9181da30e5cc692dec7cfd53feb71f
2019-03-20invisispec-1.0 sourceIru Cai
2018-12-11cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctorTony Gutierrez
Change 9af1214 added a new ctor to the LSQUnit, however there is a typo/bug because it sizes the SQEntries member variable to lqEntries + 1, as opposed to sqEntries + 1. This change corrects the issue by using sqEntries. Change-Id: I19dfaa5c0e335bd7b84343a92034147d7c5d914e Reviewed-on: https://gem5-review.googlesource.com/c/15015 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-12-04base, sim: Add missing destructorsNikos Nikoleris
Derived classes with virtual functions need to define a virtual destructor or a protected destructor otherwise calling the base class destructor has undefined behavior. This change adds a virtual distructor in the base class. Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14815 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-12-03cpu: Change raw pointers to STL ContainersRekai Gonzalez-Alberquilla
This patch changes two members from being raw pointers to being STL containers. The reason behind, other than cleanlyness and arguable OO best practices is that containers have more intronspections capabilities than naked pointers do, as the size is known. Using STL containers adds little overhead and eases the automation of process during debugging (gdb). Change-Id: I4d9d3eedafa8b5e50ac512ea93b458a4200229f2 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13126 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-28cpu: Added new stats to TAGE and LTAGE branch predictorsPau Cabre
They are basically used to tell wich component of the predictor is providing the prediction and whether it is correct or wrong Change-Id: I7b3db66535f159091f1b37d70c2d942d50b20fb2 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14535 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-28cpu: split LTAGE implementation into a base TAGE and a derived LTAGEPau Cabre
The new derived LTAGE is equivalent to the original LTAGE implementation The default values of the TAGE branch predictor match the settings of the 8C-TAGE configuration described in https://www.jilp.org/vol8/v8paper1.pdf Change-Id: I8323adbfd5c9a45db23cfff234218280e639f9ed Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14435 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-28cpu,arch-arm: Initialise data membersRekai Gonzalez-Alberquilla
The value that is not initialized has a bogus value that manifests when using some debug-flags what makes the usage of tracediff a bit more challenging. In addition, while debugging with other techniques, it introduces the problem of understanding if the value of a field is 'intended' or just an effect of the lack of initialisation. Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13125 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-27arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.Gabe Black
Neither assert(0) nor assert(false) give any hint as to why control getting to them is bad, and their more descriptive versions, assert(0 && "description") and assert(false && "description"), jury rig assert to add an error message when the utility function panic() already does that directly with better formatting options. This change replaces that flavor of call to assert with panic, except in the actual code which processes the formatting that panic uses (to avoid infinitely recurring error handling), and in some *.sm files since I don't know what rules those have to follow and don't want to accidentaly break them. Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0 Reviewed-on: https://gem5-review.googlesource.com/c/14636 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-22cpu: Made LTAGE parameters configurablePau Cabre
This includes TAGE tag sizes, TAGE table sizes, U counters reset period, loop predictor associativity, path history size, the USE_ALT_ON_NA size and the WITHLOOP size Change-Id: I935823f0a5794f5d55b744263798897a813dc1bd Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14417 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-22cpu: Fixed useful counter handling in LTAGEPau Cabre
Increased to 2 bits of useful counter per TAGE entry as described in the LTAGE paper (and made the size configurable) Changed how the useful counters are incremented/decremented as described in the LTAGE paper Change-Id: I8c692cc7c180d29897cb77781681ff498a1d16c8 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14215 Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-22cpu: Fixes on the loop predictor part of LTAGEPau Cabre
Fixed the following fields of the loop predictor entries as described on the LTAGE paper: - Age counter (it was 3 bits and it should be 8 bits) - Tag (it was 16 bits and it should be 14 bits). Also some times it used int variables and some times uint16_t, leading to wrong behaviour - Confidence counter (it was 2 bits ins some parts of the code and 3 bits in some other parts. It should be 2 bits) - Iteration counters (they were 16 bits and they should be 14 bits) All the new sizes are now configurable Change-Id: I8884c7454c1e510b65160eb4d5749d3259d34096 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14216 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-17cpu: Fix LTAGE max number of allocations on updatePau Cabre
The LTAGE paper states that only one TAGE entry can be allocated when updating Change-Id: I6cfb4d80ce835e93d4bf5099ef88a7d425abaddd Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14195 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-17configs: Added an option for choosing branch predictor typePau Cabre
Added the parameter "--bp-type" to set the branch predictor type Added the parameter "--list-bp-types" to list all the available branch predictor types Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14015 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
Summary: Usage of const DynInstPtr& when possible and introduction of move operators to RefCountingPtr. In many places, scoped references to dynamic instructions do a copy of the DynInstPtr when a reference would do. This is detrimental to performance. On top of that, in case there is a need for reference tracking for debugging, the redundant copies make the process much more painful than it already is. Also, from the theoretical point of view, a function/method that defines a convenience name to access an instruction should not be considered an owner of the data, i.e., doing a copy and not a reference is not justified. On a related topic, C++11 introduces move semantics, and those are useful when, for example, there is a class modelling a HW structure that contains a list, and has a getHeadOfList function, to prevent doing a copy to an internal variable -> update pointer, remove from the list -> update pointer, return value making a copy to the assined variable -> update pointer, destroy the returned value -> update pointer. Change-Id: I3bb46c20ef23b6873b469fd22befb251ac44d2f6 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13105 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-14cpu: Fixed ratio of pred to hyst bits for LTAGE BimodalPau Cabre
The LTAGE paper states 1 hyst bit shared for 4 pred bits. Made this ratio configurable use 4 by default. Also changed the Bimodal structure to use two std::vector<bool> (one for pred and one for hyst bits) Change-Id: I6793e8e358be01b75b8fd181ddad50f259862d79 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14120 Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-13cpu: Fixed PC shifting on LTAGE branch predictorPau Cabre
The PC needs to be shifted according to the instShiftAmt parameter Change-Id: I272619c093695b56cf7f8ff7163e3b5d23205d16 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14035 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09cpu: Fix MinorCPU executing Crypto InstructionsGiacomo Travaglini
Crypto instruction classes added to the MinorDefaultFloatSimdFU. Change-Id: I0cd4aa422bec74285595312a8cf01f5f425a82cd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13251 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-09arch-arm: AArch32 Crypto AESMatt Horsnell
This patch implements the AArch32 AES instructions from the Crypto extension. Change-Id: I51e6deda748b0c26135bcfe9d0c7128f3af91f3d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Matt Horsnell <matt.horsnell@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13248 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: AArch32 Crypto SHAMatt Horsnell
This patch implements the AArch32 secure hashing instructions from the Crypto extension. Change-Id: Iaba8424ab71800228a9aff039d93f5c35ee7d8e5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13247 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01cpu: Fix typo in header guard for Noncaching cpuGiacomo Travaglini
Change-Id: If8ec5f5f49e99d4989658273723b943dd8df84c6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13144 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-13Fix SConstruct for asan buildEarl Ou
Sometimes it's easier to debug gem5 built with ASan enabled. This CL fixes some build error when using --with-asan. Bug: None Test: ./scripts/build_gem5 --with-asan --with-ubsan build/ARM/gem5.debug Change-Id: Iaaaaebc3f25749e11f97bf454ddd0153b3de56e7 Reviewed-on: https://gem5-review.googlesource.com/12511 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
The AtomicSimpleCPU used to be able to access memory directly to speed up simulation if no caches are used. This is fine as long as no switching between CPU models is required. In order to switch to a new CPU model that requires caches, we currently need to checkpoint the system and restore it into a new configuration. The new 'atomic_noncaching' memory mode provides a solution that avoids this issue since caches are bypassed in this mode. This changeset removes the old fastmem option from the AtomicSimpleCPU and introduces a new CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU. The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU used to use when accessing memory in when fastmem was enabled. This changeset also introduces a new switcheroo test that tests switching between a NonCachingSimpleCPU and a TimingSimpleCPU with caches. Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12419 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-24cpu: Stream/SubstreamID support in TrafficGenGiacomo Travaglini
This patch is adding support for generating memory requests which set the StreamID/SubstreamID field, so that is possible to emulate devices attached to an external IOMMU/SMMU with a Traffic generator. Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12188
2018-08-24cpu: Turn BaseTrafficGen numSuppressed into a statMichiel W. van Tol
This is changing numSuppressed from being a warn only variable into a Stat so that it is visible at the end of simulation. Change-Id: I934782e796c898bfc0e773cc88c597a68e403272 Reviewed-on: https://gem5-review.googlesource.com/11849 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-08-21misc: Appease GCC 8Jason Lowe-Power
GCC 8 adds a number of new warnings to -Wall which generate errors. - Fix memset to 0 for structs by adding casts. - Fix cast with const when the const was ignored. - Fix catch a polymorphic type by value We now compile with GCC 8! Change-Id: Iab70ce11190eee67608fc25c0bedff170152b153 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/11949 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2018-08-17scons,ruby: do not generate unnecessary filesBrandon Potter
Do not generate garnet tester file or Ruby debug headers without a Ruby protocol (i.e. PROTOCOL=None). It makes no sense to include these files into the build when there will be no protocol to utilize them. Change-Id: I8db4dd532f60008217a10c88a2e089f85df9d104 Reviewed-on: https://gem5-review.googlesource.com/8381 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-10cpu: Add hash functionality for RegId classBradley Wang
Having a hash function defined within the header will allow all classes using RegId to use the class as a Key in a STL unordered_map. Change-Id: I32fd302a087c74e844dcbfce93fef9d0ed98d6bf Signed-off-by: Bradley Wang <radwang@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/11870 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-10cpu: Removed unnecessary file reg_class_impl.hhBradley Wang
Previously, reg_class_impl.hh was added in order to prevent a cyclic dependency between it and the_isa.hh (See http://reviews.gem5.org/r/3754). It was determined that this was not necessary. The two files had almost entirely the same includes, and the current test-suite including multiple gcc and clang compilers on both MacOS and Linux successfully built the library with all functionality moved into the reg_class.hh file. Change-Id: I0319e187b9eb280726a003951bb1ce315ffe17f5 Signed-off-by: Bradley Wang <radwang@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/11869 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-25cpu: Warn when (un)serializing a traffic generatorGiacomo Travaglini
When checkpointing a system with a traffic generator, a warning is produced so that the user is reminded serialization does not keep all the traffic generator internal state. Change-Id: I3c49c912c9ff3a4208f55b2da0a88fc694147280 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11831 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-25cpu: Allow creation of traffic gen from generic SimObjectsGiacomo Travaglini
This patch allows to instantiate a Traffic generator starting from a generic SimObject, so that linking to a BaseTrafficGen only is no longer mandatory. This permits SimObjects different than a BaseTrafficGen to instantiate generators and to manually specify the MasterID they will be using when generating memory requests. Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11789 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-07-24cpu-o3: Missing freeing the heads of DepGraph in IQ squashingHanhwi Jang
Free the squahsed instructions' heads of DepGraph in IQ squashing In a system with large register file (ex.2048), the number of DynInst hits the hardcoded limit (1500). This is caused by missing freeing the heads of DepGraph in IQ. IQ only clears out the heads when instructions reach writeback stage. If a instruction is squashed before writeback stage, its head of dependency graph, which holds the instruction's DynInstPtr, would not be cleared out. This prevents freeing the DynInst of the squahsed instruction even after it is committed. Change-Id: I05b3db93cb6ad8960183d7ae765149c7f292e5b3 Reviewed-on: https://gem5-review.googlesource.com/7481 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-13cpu: Add a Python-enabled traffic generatorAndreas Sandberg
The current traffic generator relies on a configuration file that describes a small machine to generate stimuli. This configuration file is usually generated by the gem5 Python configuration. This creates an unnecessary and fragile step. This changeset introduces a Python-based trace module. When instantiated, the module exposes a start method that takes an iterable object as a parameter (e.g., a generator). The iterable object is expected to represent a list of generators that will be run one after the other. For example: system.tgen = PyTrafficGen() m5.instantiate() def trace(): yield system.tgen.createIdle(1000) yield system.tgen.createExit(0) system.tgen.start(trace()) Change-Id: I58e60ca517e86c197859f4daaa67750066abdc1c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11518 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-07-13cpu: Support trace termination in BaseTrafficGenAndreas Sandberg
Make the BaseTrafficGen handle cases where getNextPacket() can't find a new packet and returns NULL. In that case, assume the generator has run out of packets and switch to the next generator. Change-Id: I5ca6ead550005812fb849ed9ce6b5007a65ddfa7 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11517 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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