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path: root/src/cpu
AgeCommit message (Expand)Author
2014-09-03cpu: Fix SMT scheduling issue with the O3 cpuMitch Hayenga
2014-09-03cpu: Fix incorrect speculative branch predictor behaviorMitch Hayenga
2014-09-03cpu: Add a fetch queue to the o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 front-end pipeline interlock behaviorMitch Hayenga
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-09-01mem: change the namespace Message to ProtoMessageNilay Vaish
2014-09-01ruby: eliminate type TimeNilay Vaish
2014-08-13scons: Build the branch predictor for all CPUsAndreas Sandberg
2014-08-13cpu: Don't forward declare RefCountingPtrAndreas Sandberg
2014-08-13cpu: Modernise the branch predictor (STL and C++11)Andreas Hansson
2014-08-10cpu: Ensure the traffic generator suppresses non-memory packetsAndreas Hansson
2014-07-23cpu: `Minor' in-order CPU modelAndrew Bardsley
2014-06-30cpu: implement a bi-mode branch predictorAnthony Gutierrez
2014-06-21o3: make dispatch LSQ full check more selectiveBinh Pham
2014-06-21o3: split load & store queue full cases in renameBinh Pham
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-05-23cpu: o3: remove stat totalCommittedInstsNilay Vaish
2014-05-09cpu: Useful getters for ActivityRecorderAndrew Bardsley
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
2014-05-09cpu: Timebuf const accessorsAndrew Bardsley
2014-05-09arch, arm: Preserve TLB bootUncacheability when switching CPUsGeoffrey Blake
2014-05-09cpu: add more instruction mix statisticsCurtis Dunham
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-04-23cpu: Fix setTranslateLatency() bug for squashed instructionsMitchell Hayenga
2014-04-01cpu: Fix case where o3 lsq could print out uninitialized dataMitch Hayenga
2014-04-23cpu: Add O3 CPU width checksDam Sunwoo
2014-04-19o3: Fix occupancy checks for SMTFaissal Sleiman
2014-04-09kvm, x86: Add initial support for multicore simulationAndreas Sandberg
2014-03-25cpu: o3: lsq: Fix TSO implementationMarco Elver
2014-03-23cpu: DRAM Traffic GeneratorNeha Agarwal
2014-03-23cpu: Add basic check to TrafficGen initial stateStan Czerniawski
2014-03-16kvm: Clean up signal handlingAndreas Sandberg
2014-03-16kvm: x86: Adjust PC to remove the CS segment base addressAndreas Sandberg
2014-03-16kvm: x86: Add support for x86 INIT and STARTUP handlingAndreas Sandberg
2014-03-12alpha: Small removal of dead comments/code from alpha ISAPaul Rosenfeld
2014-03-07cpu: Make CPU and ThreadContext getters constAndreas Hansson
2014-03-07scons: Fixes uninitialized warnings issued by clangMitch Hayenga
2014-03-03kvm: x86: Always assume segments to be usableAndreas Sandberg
2014-03-03kvm: Initialize signal handlers from startupThread()Andreas Sandberg
2014-03-01cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPUChristopher Torng
2014-02-20kvm: Add support for multi-system simulationAndreas Sandberg
2014-02-09cpu: simple: Add support for using branch predictorsAndreas Sandberg
2014-01-29cpu: fix bug when TrafficGen deschedules eventXiangyu Dong
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2014-01-24checker: CheckerCPU handling of MiscRegs was incorrectGeoffrey Blake
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
2014-01-24cpu: Add support for Memory+Barrier instruction types in O3 cpu.Giacomo Gabrielli
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
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