| Age | Commit message (Expand) | Author |
|---|
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-25 | cpu, arch, arch-arm: Wire unused VecElem code in the O3 model | Giacomo Travaglini |
| 2019-01-25 | cpu: O3 rename using the flatIndex instead of index | Giacomo Travaglini |
| 2019-01-25 | cpu: Fix VecElemClass bugs in cpu models | Giacomo Travaglini |
| 2019-01-25 | cpu: Add VecElem entries in MinorCPU Scoreboard | Giacomo Travaglini |
| 2019-01-24 | cpu-o3: O3 LSQ Generalisation | Rekai Gonzalez-Alberquilla |
| 2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
| 2019-01-17 | cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum | Nikos Nikoleris |
| 2019-01-17 | cpu-o3: Make the smtROBPolicy a Param.ScopedEnum | Nikos Nikoleris |
| 2019-01-17 | cpu-o3: Make the smtIQPolicy a Param.ScopedEnum | Nikos Nikoleris |
| 2019-01-17 | cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum | Nikos Nikoleris |
| 2019-01-17 | cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum | Nikos Nikoleris |
| 2019-01-16 | cpu: dev: sim: gpu-compute: Banish some ISA specific register types. | Gabe Black |
| 2019-01-15 | cpu: Fix usage of setArchVecElem | Giacomo Travaglini |
| 2018-12-22 | cpu: Stop using unions to store FP registers. | Gabe Black |
| 2018-12-20 | arch, cpu: Remove float type accessors. | Gabe Black |
| 2018-12-11 | cpu: Fixed typos in parameter/stats descriptions | Pau Cabre |
| 2018-12-11 | cpu: Added parameters to enable/disable features in LTAGE | Pau Cabre |
| 2018-12-11 | cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor | Tony Gutierrez |
| 2018-12-04 | base, sim: Add missing destructors | Nikos Nikoleris |
| 2018-12-03 | cpu: Change raw pointers to STL Containers | Rekai Gonzalez-Alberquilla |
| 2018-11-28 | cpu: Added new stats to TAGE and LTAGE branch predictors | Pau Cabre |
| 2018-11-28 | cpu: split LTAGE implementation into a base TAGE and a derived LTAGE | Pau Cabre |
| 2018-11-28 | cpu,arch-arm: Initialise data members | Rekai Gonzalez-Alberquilla |
| 2018-11-27 | arch, base, cpu, gpu, mem: Replace assert(0 or false with panic. | Gabe Black |
| 2018-11-22 | cpu: Made LTAGE parameters configurable | Pau Cabre |
| 2018-11-22 | cpu: Fixed useful counter handling in LTAGE | Pau Cabre |
| 2018-11-22 | cpu: Fixes on the loop predictor part of LTAGE | Pau Cabre |
| 2018-11-17 | cpu: Fix LTAGE max number of allocations on update | Pau Cabre |
| 2018-11-17 | configs: Added an option for choosing branch predictor type | Pau Cabre |
| 2018-11-16 | cpu: Fix the usage of const DynInstPtr | Rekai Gonzalez-Alberquilla |
| 2018-11-14 | cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal | Pau Cabre |
| 2018-11-13 | cpu: Fixed PC shifting on LTAGE branch predictor | Pau Cabre |
| 2018-10-09 | cpu: Fix MinorCPU executing Crypto Instructions | Giacomo Travaglini |
| 2018-10-09 | arch-arm: AArch32 Crypto AES | Matt Horsnell |
| 2018-10-09 | arch-arm: AArch32 Crypto SHA | Matt Horsnell |
| 2018-10-01 | cpu: Fix typo in header guard for Noncaching cpu | Giacomo Travaglini |
| 2018-09-13 | Fix SConstruct for asan build | Earl Ou |
| 2018-09-12 | cpu: Replace the fastmem with a new CPU model | Andreas Sandberg |
| 2018-08-24 | cpu: Stream/SubstreamID support in TrafficGen | Giacomo Travaglini |
| 2018-08-24 | cpu: Turn BaseTrafficGen numSuppressed into a stat | Michiel W. van Tol |
| 2018-08-21 | misc: Appease GCC 8 | Jason Lowe-Power |
| 2018-08-17 | scons,ruby: do not generate unnecessary files | Brandon Potter |
| 2018-08-10 | cpu: Add hash functionality for RegId class | Bradley Wang |
| 2018-08-10 | cpu: Removed unnecessary file reg_class_impl.hh | Bradley Wang |
| 2018-07-25 | cpu: Warn when (un)serializing a traffic generator | Giacomo Travaglini |
| 2018-07-25 | cpu: Allow creation of traffic gen from generic SimObjects | Giacomo Travaglini |
| 2018-07-24 | cpu-o3: Missing freeing the heads of DepGraph in IQ squashing | Hanhwi Jang |
| 2018-07-13 | cpu: Add a Python-enabled traffic generator | Andreas Sandberg |
