| Age | Commit message (Expand) | Author |
|---|
| 2018-07-13 | cpu: Support trace termination in BaseTrafficGen | Andreas Sandberg |
| 2018-07-13 | cpu: Unify error handling for address generators | Andreas Sandberg |
| 2018-07-13 | cpu: Split the traffic generator into two classes | Andreas Sandberg |
| 2018-06-28 | cpu: Remove reduntant protobuf includes | Andreas Sandberg |
| 2018-06-21 | cpu: Fix bug introduced by RequestPtr type change | Giacomo Travaglini |
| 2018-06-14 | cpu: Prevent suspended TimingSimple CPUs from fetching next instructions | Tuan Ta |
| 2018-06-14 | cpu: add a new instruction type 'Atomic' | Tuan Ta |
| 2018-06-14 | cpu-minor: Remove redundant thread startup call | Andreas Sandberg |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-06-11 | misc: Substitute pointer to Request with aliased RequestPtr | Giacomo Travaglini |
| 2018-05-29 | cpu: Avoid unnecessary dynamic_pointer_cast in atomic model | Giacomo Travaglini |
| 2018-04-27 | sim,cpu,mem,arch: Introduced MasterInfo data structure | Giacomo Travaglini |
| 2018-03-27 | cpu: Remove ExtMachInst typedefs from the O3 CPU model. | Gabe Black |
| 2018-03-27 | arch: cpu: Make the ExtMachInst type a template argument in InstMap. | Gabe Black |
| 2018-03-27 | cpu: Stop extracting inst_flags from the machInst. | Gabe Black |
| 2018-03-26 | cpu: Use the new asBytes function in the protobuf inst tracer. | Gabe Black |
| 2018-03-26 | arch: Add a virtual asBytes function to the StaticInst class. | Gabe Black |
| 2018-03-23 | ruby: Make sure addresses print in hex | Jason Lowe-Power |
| 2018-03-06 | scons: Switch from the print statement to the print function. | Gabe Black |
| 2018-02-20 | cpu-o3: Don't add non-speculative mem barriers to the IQ twice | Andreas Sandberg |
| 2018-02-05 | cpu: MinorCPU handling IsSquashAfter flag | Giacomo Travaglini |
| 2018-01-29 | arm: DT autogeneration - Generate cpus node | Glenn Bergmans |
| 2018-01-12 | sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). | Xiaoyu Ma |
| 2018-01-11 | cpu: Make the CPU's TLB parameter a BaseTLB. | Gabe Black |
| 2018-01-10 | style: change C/C++ source permissions to noexec | BKP |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-09 | cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults. | Gabe Black |
| 2018-01-09 | cpu: Add a NotAnInst flag to the BaseDynInst class. | Gabe Black |
| 2018-01-09 | cpu, power: Get rid of the remnants of the EA computation insts. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-22 | cpu: Use the generic nop static inst instead of decoding the arch version. | Gabe Black |
| 2017-12-22 | cpu: Add a pointer to a generic Nop StaticInst. | Gabe Black |
| 2017-12-20 | cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh. | Gabe Black |
| 2017-12-19 | cpu-tester: Added ExitGen to TrafficGen | Riken Gohil |
| 2017-12-19 | cpu-tester: Refactoring traffic generators into separate files. | Riken Gohil |
| 2017-12-14 | misc: Updates for gcc7.2 for x86 | Jason Lowe-Power |
| 2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-08 | x86,misc: add additional info on faulting X86 instruction, fetched PC | Matt Sinclair |
| 2017-12-05 | cpu: Add support for CMOs in the cpu models | Nikos Nikoleris |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-11-29 | cpu: Don't override ISA if provided by user | Andreas Sandberg |
| 2017-11-29 | cpu-minor: Add missing instruction stats | David Guillen Fandos |
| 2017-11-28 | cpu-o3: Add missing vector stat initializers | Andreas Sandberg |
| 2017-11-21 | cpu, cpu, sim: move Cycle probe update | Jose Marinho |
| 2017-11-21 | cpu-o3: Prevent cpu from suspending if it is already draining | Nikos Nikoleris |
| 2017-11-20 | cpu: Make automatic transition to OFF optional | Jose Marinho |
| 2017-11-20 | pwr: Adds logic to enter power gating for the cpu model | Anouk Van Laer |
| 2017-11-14 | cpu, probe: Fix elastic trace register dependency | Radhika Jagtap |
| 2017-10-19 | cpu-o3: Add M5_VAR_USED to variable | Jason Lowe-Power |
