Age | Commit message (Expand) | Author |
2007-09-28 | Update statistics to use cycles properly instead of ticks | Ali Saidi |
2007-09-25 | Merge with head. | Gabe Black |
2007-09-25 | SPARC: Fix a stupid mistake which was breaking the SPARC regressions. | Gabe Black |
2007-09-24 | X86: Get X86_FS to compile. | Gabe Black |
2007-09-19 | X86: Put in the foundation for x87 stack based fp registers. | Gabe Black |
2007-09-04 | X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actua... | Gabe Black |
2007-08-31 | X86: Get x86 to compile again after the simobject constructor change. | Gabe Black |
2007-08-30 | Fix miscellaneous small typos. | Miles Kaufmann |
2007-08-30 | params: Deprecate old-style constructors; update most SimObject constructors. | Miles Kaufmann |
2007-08-26 | Merge with head | Gabe Black |
2007-08-26 | O3 CPU: Remove alignment check from dynamic instruction read/write functions. | Gabe Black |
2007-08-26 | Simple CPU: Don't trace instructions that fault. Otherwise they show up twice. | Gabe Black |
2007-08-26 | Simple CPU: Added code that will split requests that cross block boundaries i... | Gabe Black |
2007-08-26 | Simple CPU: Make sure only instructions which complete without faulting are c... | Gabe Black |
2007-08-26 | Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. | Gabe Black |
2007-08-21 | Merge with head. | Gabe Black |
2007-08-21 | o3: Fix for retry ID bug. | Kevin Lim |
2007-08-13 | O3: Set up the predicted npc and nnpc for a fault carrying noop so that it do... | Gabe Black |
2007-08-13 | Move the "translate" member functions back into the base o3 class. | Gabe Black |
2007-08-08 | Added fastmem option. | Vincentius Robby |
2007-08-08 | Port, StaticInst: Revert unnecessary changes. | Vincentius Robby |
2007-08-08 | alpha: Make the TLB cache to actually work. | Vincentius Robby |
2007-08-07 | Merge with head. | Gabe Black |
2007-08-07 | X86: Make a microcode branch microop. | Gabe Black |
2007-08-04 | switching: turn on profiling after a switch if there's an event | Nathan Binkert |
2007-08-04 | SimpleCPU: Add some DPRINTFs | Nathan Binkert |
2007-08-04 | StaticInst: Fix decode cache initialization. Cache functionality was negated. | Vincentius Robby |
2007-08-01 | Merge with head. | Gabe Black |
2007-08-01 | X86: Reorganize the native tracing code. | Gabe Black |
2007-07-31 | Add a flag to indicate an instruction triggers a syscall in SE mode. | Gabe Black |
2007-07-31 | Merge from head. | Steve Reinhardt |
2007-07-30 | Fix problem with tracer not being initialized. | Gabe Black |
2007-07-29 | Merge Gabe's changes from head. | Steve Reinhardt |
2007-07-29 | BsaeCPU: Get rid of some bad DPRINTFs. | Steve Reinhardt |
2007-07-29 | X86: Fix register ordering. | Gabe Black |
2007-07-28 | Turn the instruction tracing code into pluggable sim objects. | Gabe Black |
2007-07-28 | AtomicSimpleCPU: fix inadvertent loss of endian conversion on read. | Steve Reinhardt |
2007-07-27 | cache/memtest: fixes for functional accesses. | Steve Reinhardt |
2007-07-26 | Merge python and x86 changes with cache branch | Nathan Binkert |
2007-07-26 | X86: Fix argument register indexing. | Gabe Black |
2007-07-23 | Major changes to how SimObjects are created and initialized. Almost all | Nathan Binkert |
2007-07-23 | Fix WriteReq/StoreCondReq setting in O3. | Steve Reinhardt |
2007-07-15 | Fix bug with timing snoop upcalls to MemTest object. | Steve Reinhardt |
2007-07-15 | Fix up a bunch of multilevel coherence issues. | Steve Reinhardt |
2007-07-15 | Fix problem with unset max_loads in memtest. | Steve Reinhardt |
2007-07-02 | Couple more minor bug fixes for FS timing mode. | Steve Reinhardt |
2007-07-02 | Fix a couple LL/SC bugs that only affected timing mode. | Steve Reinhardt |
2007-06-30 | Make CPU models use new LoadLockedReq/StoreCondReq commands. | Steve Reinhardt |
2007-06-30 | Event descriptions should not end in "event" | Steve Reinhardt |
2007-06-30 | Get rid of Packet result field. Error responses are | Steve Reinhardt |