| Age | Commit message (Expand) | Author |
|---|
| 2018-03-06 | scons: Switch from the print statement to the print function. | Gabe Black |
| 2018-02-20 | cpu-o3: Don't add non-speculative mem barriers to the IQ twice | Andreas Sandberg |
| 2018-02-05 | cpu: MinorCPU handling IsSquashAfter flag | Giacomo Travaglini |
| 2018-01-29 | arm: DT autogeneration - Generate cpus node | Glenn Bergmans |
| 2018-01-12 | sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). | Xiaoyu Ma |
| 2018-01-11 | cpu: Make the CPU's TLB parameter a BaseTLB. | Gabe Black |
| 2018-01-10 | style: change C/C++ source permissions to noexec | BKP |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-09 | cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults. | Gabe Black |
| 2018-01-09 | cpu: Add a NotAnInst flag to the BaseDynInst class. | Gabe Black |
| 2018-01-09 | cpu, power: Get rid of the remnants of the EA computation insts. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-22 | cpu: Use the generic nop static inst instead of decoding the arch version. | Gabe Black |
| 2017-12-22 | cpu: Add a pointer to a generic Nop StaticInst. | Gabe Black |
| 2017-12-20 | cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh. | Gabe Black |
| 2017-12-19 | cpu-tester: Added ExitGen to TrafficGen | Riken Gohil |
| 2017-12-19 | cpu-tester: Refactoring traffic generators into separate files. | Riken Gohil |
| 2017-12-14 | misc: Updates for gcc7.2 for x86 | Jason Lowe-Power |
| 2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-08 | x86,misc: add additional info on faulting X86 instruction, fetched PC | Matt Sinclair |
| 2017-12-05 | cpu: Add support for CMOs in the cpu models | Nikos Nikoleris |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-11-29 | cpu: Don't override ISA if provided by user | Andreas Sandberg |
| 2017-11-29 | cpu-minor: Add missing instruction stats | David Guillen Fandos |
| 2017-11-28 | cpu-o3: Add missing vector stat initializers | Andreas Sandberg |
| 2017-11-21 | cpu, cpu, sim: move Cycle probe update | Jose Marinho |
| 2017-11-21 | cpu-o3: Prevent cpu from suspending if it is already draining | Nikos Nikoleris |
| 2017-11-20 | cpu: Make automatic transition to OFF optional | Jose Marinho |
| 2017-11-20 | pwr: Adds logic to enter power gating for the cpu model | Anouk Van Laer |
| 2017-11-14 | cpu, probe: Fix elastic trace register dependency | Radhika Jagtap |
| 2017-10-19 | cpu-o3: Add M5_VAR_USED to variable | Jason Lowe-Power |
| 2017-10-13 | cpu-o3: Check predication before the SQ size for a debug print | Nikos Nikoleris |
| 2017-10-13 | cpu-o3: Avoid early checker verification for store conditionals | Nikos Nikoleris |
| 2017-09-11 | stats: Get rid of some kernel stats related cruft. | Gabe Black |
| 2017-09-06 | cpu: Fix bi-mode branch predictor thresholds | Rico Amslinger |
| 2017-09-01 | cpu-minor: Fix for addr range coverage calculation | Pau Cabre |
| 2017-08-30 | cpu-o3: fix data pkt initialization for split load | Matthias Hille |
| 2017-08-01 | kvm: Add a helper method to access device event queues | Andreas Sandberg |
| 2017-08-01 | cpu, kvm: Fix deadlock issue when resuming a drained system | Andreas Sandberg |
| 2017-07-19 | cpu: Add missing rename of vector registers in the O3 CPU | Rekai Gonzalez-Alberquilla |
| 2017-07-17 | cpu,o3: Fixed checkpointing bug occuring in the o3 CPU | Anouk Van Laer |
| 2017-07-12 | testers: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | kvm, mem: Refactor some Event subclasses into lambdas | Sean Wilson |
| 2017-07-12 | cpu: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | cpu, sim: Add param to force CPUs to wait for GDB | Jose Marinho |
| 2017-07-07 | kvm, arm: Don't forward IRQ/FIQ when using the kernel's GIC | Andreas Sandberg |
| 2017-07-05 | arch: ISA parser additions of vector registers | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Result refactoring | Rekai Gonzalez-Alberquilla |
